D16450 - Configurable UART
Block Diagram
Overview
The D16450 is a soft core of the Universal Asynchronous Receiver/Transmitter (UART), functionally identical to the TL16C450. It performs serial-to-parallel conversion on data characters received from a peripheral device or a MODEM, but also parallel-to-serial conversion on data characters received from the CPU. The CPU can read a complete status of the UART at any time, during the functional operation. Reported information status includes the type and a condition of transfer operations being performed by the UART, as well as any error conditions (parity, overrun, framing or break interrupt). The D16450 includes a programmable baud rate generator, which is capable of dividing the timing reference clock input by divisors of 1 to (216-1), and producing a 16 clock for driving the internal transmitter logic. Provisions are also included to use this 16 clock to drive the receiver logic. Our proprietary solution has also complete MODEM control capability and a processor-interrupt system
Features
- Software compatible with 16450 UART; Configuration capability; Separate configurable BAUD clock line
- Majority Voting Logic; Adds or deletes standard asynchronous communication bits (start, stop and parity) to or from the serial data
- Independently controlled transmit, receive, line status and data set interrupts; False start bit detection
- 16 bit programmable baud generator; Independent receiver clock input; MODEM control functions (CTS, RTS, DSR, DTR, RI and DCD)
IP Quality Metrics
| Basic | |
|---|---|
| Year IP was first released | 2003 |
| Latest version of Quartus supported | 15.1 |
| Altera Customer Use | |
| IP has been successfully implemented in production with at least one customer | Y |
| Deliverables | |
Customer deliverables include the following:
|
Y |
| Any additional customer deliverables provided with IP | NA |
| Parameterization GUI allowing end user to configure IP | Y |
| IP core is enabled for OpenCore Plus Support | Y |
| Source language | Verilog; VHDL |
| Testbench language | Verilog; VHDL |
| Software drivers provided | Y |
| Driver OS support | TBD |
| Implementation | |
| User Interface | AXI; Avalon-MM |
| IP-XACT Metadata included | N |
| Verification | |
| Simulators supported | ModelSim |
| Hardware validated | Y. Altera Board Name DE1, DE2 |
| Industry standard compliance testing performed | N |
| If No, is it planned? | Y |
| Interoperability | |
| IP has undergone interoperability testing | N |
| Interoperability reports available | Y |
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