USB3.0 Host IP core
Block Diagram
Overview
USB3.0 (Host) IP Core is ideal for use in a USB3.0 supported device system which require highbandwidth up to 5.0Gbps. This IP Core will process almost all USB3.0 protocols by hardware. It achieves processing by low-end CPU.This IPcore provide link layer, protocol layer. Physical layer interfaces to PHY chip by TI. DesignGateway provide 1-hour limited sof file for Intel® FPGA development kits. You can evaluate the performance before purchasing the IP core. More information from here http://www.dgway.com/USB3-IP_A_E.html
Features
- Compliant with USB3.0 specification Revision1.0.
- Implements link and protocol layers. Physical layer interfaces to PHY chip by TI (TUSB1310A)
- Simple transaction interface with Host processor or DMA interface
- Free demo SOF file for evaluation on Intel board.
- Reference design available on Cyclone®IV GX, CycloneVE, Arria®V GX Development Kit
IP Quality Metrics
| Basic | |
|---|---|
| Year IP was first released | 2011 |
| Latest version of Quartus supported | 15.1 |
| Altera Customer Use | |
| IP has been successfully implemented in production with at least one customer | Y |
| Deliverables | |
Customer deliverables include the following:
|
Y |
| Any additional customer deliverables provided with IP | Reference Design |
| Parameterization GUI allowing end user to configure IP | N |
| IP core is enabled for OpenCore Plus Support | N |
| Source language | VHDL |
| Testbench language | VHDL |
| Software drivers provided | N |
| Driver OS support | N/A |
| Implementation | |
| User Interface | Other: Customized |
| IP-XACT Metadata included | N |
| Verification | |
| Simulators supported | Modelsim Altera Edition |
| Hardware validated | Y. Altera Board Name Cyclone IV GX, Cyclone V E, Arria V GX Development Kit |
| Industry standard compliance testing performed | N |
| If No, is it planned? | N |
| Interoperability | |
| IP has undergone interoperability testing | Y |
| Interoperability reports available | N |
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