TCP Offloading Engine IP core (TOE1G IP)
Block Diagram

Overview
TCP Offloading Engine(TOE1G) IP core is the epochal solution implemented without CPU. Usually TCP processing is complicated and needs an expensive high-end CPU. Because TOE1G IP core automatically takes over all functions of TCP/IP protocol which needs high-speed operation by hardware logic only. This IP product includes reference design forIntel® FPGA. It helps you to reduce development time.DesignGateway provide demo file for Intel FPGA Development Kits for evaluation. You can evaluate TOE1G IP core on real board before purchasing.For more information, visit http://www.dgway.com/TOE1G-IP_A_E.html
IP Quality Metrics
Basic | |
---|---|
Year IP was first released | 2015 |
Latest version of Quartus supported | 16.0 |
Altera Customer Use | |
IP has been successfully implemented in production with at least one customer | Y |
Deliverables | |
Customer deliverables include the following:
|
Y |
Any additional customer deliverables provided with IP | Reference Design |
Parameterization GUI allowing end user to configure IP | N |
IP core is enabled for OpenCore Plus Support | N |
Source language | VHDL |
Testbench language | VHDL |
Software drivers provided | N |
Driver OS support | N/A |
Implementation | |
User Interface | Other: Customized |
IP-XACT Metadata included | N |
Verification | |
Simulators supported | ModelSim - Intel® FPGA Edition |
Hardware validated | Y. Altera Board Name Arria10 SX, Arria V GX, Stratix V GX |
Industry standard compliance testing performed | N |
If No, is it planned? | N |
Interoperability | |
IP has undergone interoperability testing | Y |
Interoperability reports available | N |
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