TCP Offloading Engine IP core (TOE1G IP)

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireline

Evaluation Method: Source Code

Technology: Interface Protocols: Ethernet

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® V, Cyclone® V SoC

Stratix Series: Stratix® IV


TCP Offloading Engine(TOE1G) IP core is the epochal solution implemented without CPU. Usually TCP processing is complicated and needs an expensive high-end CPU. Because TOE1G IP core automatically takes over all functions of TCP/IP protocol which needs high-speed operation by hardware logic only. This IP product includes reference design forIntel® FPGA. It helps you to reduce development time.DesignGateway provide demo file for Intel FPGA Development Kits for evaluation. You can evaluate TOE1G IP core on real board before purchasing.For more information, visit


  • TCP/IP Stack Implementation By All Hardware Logic, Without CPU
  • Support Full Duplex transmission
  • Support both Server and Client mode (Passive/Active open and close)
  • Simple control interface by standard register interface
  • Reference design available on Intel FPGA Development Kits

Device Utilization and Performance

Intel Arria®10 SX (10AS066N3F40E2SGE2) Fmax=125MHz, ALMs=2,028, Block Memory bit=1,181,696 / Stratix® IV GX (EP4SGX230KF40C2) Fmax=125MHz, ALMs=2,226, Block Memory bit=1,181,696 /Arria V GX (5AGXFB3H4F35C5) Fmax=125MHz, ALMs=2,064, Block Memory bit=1,181,696 /

Getting Started

1st Step: Download free evaluation sof file from DesignGateway official website.2nd Step: Evaluate the IP core performance.3rd Step: Purchasing IP core.For more information, visit

IP Quality Metrics

Year IP was first released2015
Latest version of Quartus supported16.0
Altera Customer Use
IP has been successfully implemented in production with at least one customerY

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Any additional customer deliverables provided with IP
Reference Design
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportN
Source language
Testbench languageVHDL
Software drivers providedN
Driver OS supportN/A
User InterfaceOther: Customized
IP-XACT Metadata includedN
Simulators supportedModelSim - Intel® FPGA Edition
Hardware validated Y. Altera Board Name Arria10 SX, Arria V GX, Stratix V GX
Industry standard compliance testing performed
If No, is it planned?N
IP has undergone interoperability testing
Interoperability reports available  N

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