SATA IP core

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement

Evaluation Method: Source Code

Technology: Interface Protocols: Serial

Arria Series: Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

Stratix Series: Stratix® IV, Stratix® V


SerialATA(SATA)IP core provides link layer to implement SATA channel to Intel® FPGA devices. These support SATA-III (6Gbps) and matches with SATA-III SSDs. It can connect with SSD/HDD without PHY chip. You can develop your product in a short period because the IP core product includes the reference design with source code designed for Intel FPGA development kit. For more information, visit


  • Compliant with Serial ATA specification revision 3.0
  • Simple transaction interface with Host processor or DMA Engine
  • Support both of SATA Host and SATA Device (Applicable to SATA Peripheral development)
  • Able to evaluate on Intel FPGA development kits before purchasing the IPcore
  • Many options are available such as RAID, AHCI, Hard logic Host controller, exFAT

Device Utilization and Performance

[Implementation Statistics]Intel Arria® 10 SX (10AS066N3F40E2SGE2) Fmax=500MHz, ALMs=684, Block Memory bit=33,792[Performance]1ch: Read=516MB/sec, Write=471MB/sec4ch RAID0: Read=2019MB/sec, the transfer efficiency is 99.8%

Getting Started

1st Step: Download free evaluation sof file from DesignGateway official website.2nd Step: Adapter board is provided from DesignGateway.3rd Step: Evaluate the IP core performance.4th Step: Purchasing IP core.For more information, visit

IP Quality Metrics

Year IP was first released2014
Latest version of Quartus supported16.0
Altera Customer Use
IP has been successfully implemented in production with at least one customerY

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Any additional customer deliverables provided with IP
Reference Design
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportN
Source language
Testbench languageVHDL
Software drivers providedN
Driver OS supportN/A
User InterfaceOther: Customized
IP-XACT Metadata includedN
Simulators supportedModelSim Altera Edition
Hardware validated Y. Altera Board Name Arria V GX, Stratix V GX, Cyclone V SX SoC, Arria V ST SoC, Stratix IV GX, Arria 10 SX SoC
Industry standard compliance testing performed
If No, is it planned?N
IP has undergone interoperability testing
Interoperability reports available  N

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