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Documentation

SATA Host Controller IP core (SATA HCTL IP)

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement

Evaluation Method: Source Code

Technology: Interface Protocols: Serial

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® V, Cyclone® V SoC

Stratix Series: Stratix® V

Overview

SATA Host IP Core operating with DG SATA-IP and SATA PHY is ideal for the storage system whichdoes not have internal CPU to control SATA Device access. It is recommended to use in very high-speeddata recording system, and RAID controller.For more information, visit http://www.dgway.com/SATA-IP_A_E.html

Features

Simple user control interface
Small logic resource without Block Memory utilization
Suitable for system without CPU and DDR
Support three ATA commands for application layer, i.e. IDENTIFY DEVICE, WRITE DMA (EXT), and READ DMA (EXT)
Rerference design is included in IP core product

Device Utilization and Performance

[Implementation Statistics]Arria®V GX (5AGXFB3H4F35C4) Fmax=277 MHz, ALMs=365, Block Memory bit=0Stratix®V GX (5SGXEA7K2F40C2) Fmax=357MHz, ALMs=370, Block Memory bit=0Arria10 SX (10AS066N3F40E2SG ) Fmax=384 MHz, ALMs=385, Block Memory bit=0

Getting Started

1st Step: Download free evaluation sof file from DesignGateway website http://www.dgway.com/SATA-IP_A_E.html2nd Step: Adapter board is provided from DesignGateway.3rd Step: Evaluate the IP core performance.4th Step: Purchasing.For more information, visit http://www.dgway.com/SATA-IP_A_E.html

IP Quality Metrics

Basic
Year IP was first released	2015
Latest version of Quartus supported	16.0
Altera Customer Use
IP has been successfully implemented in production with at least one customer	Y
Deliverables
Customer deliverables include the following: Design file (encrypted source code or post-synthesis netlist) Simulation model for ModelSim Altera edition Timing and/or layout constraints Testbench or design example Documentation with revision control Readme file	Y
Any additional customer deliverables provided with IP	Reference Design
Parameterization GUI allowing end user to configure IP	N
IP core is enabled for OpenCore Plus Support	N
Source language	VHDL
Testbench language	VHDL
Software drivers provided	N
Driver OS support	N/A
Implementation
User Interface	Other: Customized
IP-XACT Metadata included	N
Verification
Simulators supported	ModelSim - Intel® FPGA Edition
Hardware validated	Y. Altera Board Name Arria10 SX, ArriaV GX, StratixV GX development kit
Industry standard compliance testing performed	N
If No, is it planned?	N
Interoperability
IP has undergone interoperability testing	Y
Interoperability reports available	N

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