SATA Host Controller IP core (SATA HCTL IP)
Block Diagram

Overview
SATA Host IP Core operating with DG SATA-IP and SATA PHY is ideal for the storage system whichdoes not have internal CPU to control SATA Device access. It is recommended to use in very high-speeddata recording system, and RAID controller.For more information, visit http://www.dgway.com/SATA-IP_A_E.html
Getting Started
IP Quality Metrics
Basic | |
---|---|
Year IP was first released | 2015 |
Latest version of Quartus supported | 16.0 |
Altera Customer Use | |
IP has been successfully implemented in production with at least one customer | Y |
Deliverables | |
Customer deliverables include the following:
|
Y |
Any additional customer deliverables provided with IP | Reference Design |
Parameterization GUI allowing end user to configure IP | N |
IP core is enabled for OpenCore Plus Support | N |
Source language | VHDL |
Testbench language | VHDL |
Software drivers provided | N |
Driver OS support | N/A |
Implementation | |
User Interface | Other: Customized |
IP-XACT Metadata included | N |
Verification | |
Simulators supported | ModelSim - Intel® FPGA Edition |
Hardware validated | Y. Altera Board Name Arria10 SX, ArriaV GX, StratixV GX development kit |
Industry standard compliance testing performed | N |
If No, is it planned? | N |
Interoperability | |
IP has undergone interoperability testing | Y |
Interoperability reports available | N |
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