SATA AHCI IP core
Block Diagram
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Supported Device Family:
Solution Type:
Overview
SATA AHCI IP core operating with SATA IP Core is suitable for the system which has the processorrunning on OS and needs to have SATA device to be the system storage. By using AHCI driver to accessAHCI IP, the system can access SATA device with full features and high speed performance. ARM onCyclone® V/Arria® V/Arria 10 SoC platform can be used to be the processor for AHCI IP, so the IP can be applied forembedded storage system, RAID application, high-speed and large capacity data acquisition systems.For more information, visit http://www.dgway.com/SATA-IP_A_E.html
Features
- Compliant with the Serial ATA Advanced Host Controller Interface (AHCI) 1.3.1
- Support up to 120 PRD entries per command
- 64-bit AXI4 bus for data interface
- Multiple ports for RAID application can be designed by using multiple SATA AHCI IP
- AHCI IP Reference design available on Cyclone® V SX SoC board/Arria® V ST SoC board/Arria 10 SX SoC board
IP Quality Metrics
| Basic | |
|---|---|
| Year IP was first released | 2015 |
| Latest version of Quartus supported | 16.0 |
| Altera Customer Use | |
| IP has been successfully implemented in production with at least one customer | Y |
| Deliverables | |
Customer deliverables include the following:
|
Y |
| Any additional customer deliverables provided with IP | Reference Design |
| Parameterization GUI allowing end user to configure IP | N |
| IP core is enabled for OpenCore Plus Support | N |
| Source language | VHDL |
| Testbench language | VHDL |
| Software drivers provided | N |
| Driver OS support | N/A |
| Implementation | |
| User Interface | Other: Customized |
| IP-XACT Metadata included | N |
| Verification | |
| Simulators supported | ModelSim Altera Edition |
| Hardware validated | Y. Altera Board Name Cyclone V SX SoC board /Arria V ST SoC board/Arria 10 SX SoC board |
| Industry standard compliance testing performed | N |
| If No, is it planned? | N |
| Interoperability | |
| IP has undergone interoperability testing | Y |
| Interoperability reports available | N |
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