DG 10GbE MAC core
Block Diagram
Features
- Super Low Latency. Tx latency = 19.2nsec, Rx latency = 44.8nsec. 1/4 compared with Intel MAC.
- Minimized resource usage. Drastically reduce resource consumption compared with Intel MAC by omitting MAC function which is not used for DG TOE/UDP10G
- Low Cost Solution. It is provided with TOE/UDP10G-IP core with small additional fee. You do not need to purchase vender's EMAC core so you can reduce
IP Quality Metrics
| Basic | |
|---|---|
| Year IP was first released | 2019 |
| Latest version of Quartus supported | 18.0 |
| Altera Customer Use | |
| IP has been successfully implemented in production with at least one customer | Y |
| Deliverables | |
Customer deliverables include the following:
|
Y |
| Any additional customer deliverables provided with IP | Reference Design |
| Parameterization GUI allowing end user to configure IP | N |
| IP core is enabled for OpenCore Plus Support | N |
| Source language | VHDL |
| Testbench language | VHDL |
| Software drivers provided | N |
| Driver OS support | N/A |
| Implementation | |
| User Interface | Other: Customized |
| IP-XACT Metadata included | N |
| Verification | |
| Simulators supported | ModelSim Altera Edition |
| Hardware validated | Y. Altera Board Name Arria 10 GX FPGA development kit |
| Industry standard compliance testing performed | N |
| If No, is it planned? | N |
| Interoperability | |
| IP has undergone interoperability testing | Y |
| Interoperability reports available | N |
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