DG 10GbE MAC core

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireline

Evaluation Method: Source Code

Technology: Interface Protocols: Ethernet

Arria Series: Intel® Arria® 10

Cyclone Series: Intel® Cyclone® 10: Intel® Cyclone® 10 GX

Overview

DG 10GbE MAC core implements the MAC layer for TOE/UDP10G-IP core. It is fully compatible with Intel MAC core. It achieves Super Low latency and High-speed networking system.

Features

  • Super Low Latency. Tx latency = 19.2nsec, Rx latency = 44.8nsec. 1/4 compared with Intel MAC.
  • Minimized resource usage. Drastically reduce resource consumption compared with Intel MAC by omitting MAC function which is not used for DG TOE/UDP10G
  • Low Cost Solution. It is provided with TOE/UDP10G-IP core with small additional fee. You do not need to purchase vender's EMAC core so you can reduce

Device Utilization and Performance

Intel Arria® 10 GX (10AX115S2F45I2SG) Fmax=156.25MHz, ALMs=1,362, Block Memory bit=0

Getting Started

1st Step: Download free evaluation sof file from DesignGateway official website / 2nd Step: Adapter board is provided from DesignGateway / 3rd Step: Evaluate the IP core performance /

IP Quality Metrics

Basic
Year IP was first released2019
Latest version of Quartus supported18.0
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Any additional customer deliverables provided with IP
Reference Design
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportN
Source language
VHDL
Testbench languageVHDL
Software drivers providedN
Driver OS supportN/A
Implementation
User InterfaceOther: Customized
IP-XACT Metadata includedN
Verification
Simulators supportedModelSim Altera Edition
Hardware validated Y. Altera Board Name Arria 10 GX FPGA development kit
Industry standard compliance testing performed
N
If No, is it planned?N
Interoperability
IP has undergone interoperability testing
Y
Interoperability reports available  N

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