40GbE TCP Offloading EngineIP core (TOE40G-IP)

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireline

Evaluation Method: Source Code

Technology: Interface Protocols: Ethernet

Arria Series: Intel® Arria® 10

Overview

40GbE TCP Off-loading Engine(TOE40G-IP) IP core is the epochal solution implemented without CPU. Generally, TCP processing is so complicated that expensive high-end CPU is required. TOE40G-IP built by pure hardwired logic can take place of such extra CPU for TCP protocol management. This IP product includes reference design for Intel FPGA. It helps you to reduce development time. DesignGateway provide demo file for Intel FPGA boards. You can evaluate TOE40G-IP core on real board before purchasing.

Features

  • TCP/IP off-loading engine for 40Gbit Ethernet
  • Supports Full Duplex communication
  • Support both Server and Client mode (Passive/Active open and close)
  • Provide free evaluation sof file for FPGA Development Kits (1 hour time limited)
  • Reference design is included in IP core product

Device Utilization and Performance

Intel Arria® 10 GX (10AX115S2F45I1SG) Fmax=322MHz, ALMs=3,656, Block Memory bit=1,179,648

Getting Started

1st Step: Download free evaluation sof file from DesignGateway official website / 2nd Step: Adapter board is provided from DesignGateway / 3rd Step: Evaluate the IP core performance /

IP Quality Metrics

Basic
Year IP was first released2019
Latest version of Quartus supported18.0
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Any additional customer deliverables provided with IP
Reference Design
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportN
Source language
VHDL
Testbench languageVHDL
Software drivers providedN
Driver OS supportN/A
Implementation
User InterfaceOther: Customized
IP-XACT Metadata includedN
Verification
Simulators supportedModelSim Altera Edition
Hardware validated Y. Altera Board Name Arria 10 GX FPGA development kit
Industry standard compliance testing performed
N
If No, is it planned?N
Interoperability
IP has undergone interoperability testing
Y
Interoperability reports available  N

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