40GbE TCP Offloading EngineIP core (TOE40G-IP)
Block Diagram
Overview
40GbE TCP Off-loading Engine(TOE40G-IP) IP core is the epochal solution implemented without CPU. Generally, TCP processing is so complicated that expensive high-end CPU is required. TOE40G-IP built by pure hardwired logic can take place of such extra CPU for TCP protocol management. This IP product includes reference design for Intel FPGA. It helps you to reduce development time. DesignGateway provide demo file for Intel FPGA boards. You can evaluate TOE40G-IP core on real board before purchasing.
IP Quality Metrics
| Basic | |
|---|---|
| Year IP was first released | 2019 |
| Latest version of Quartus supported | 18.0 |
| Altera Customer Use | |
| IP has been successfully implemented in production with at least one customer | Y |
| Deliverables | |
Customer deliverables include the following:
|
Y |
| Any additional customer deliverables provided with IP | Reference Design |
| Parameterization GUI allowing end user to configure IP | N |
| IP core is enabled for OpenCore Plus Support | N |
| Source language | VHDL |
| Testbench language | VHDL |
| Software drivers provided | N |
| Driver OS support | N/A |
| Implementation | |
| User Interface | Other: Customized |
| IP-XACT Metadata included | N |
| Verification | |
| Simulators supported | ModelSim Altera Edition |
| Hardware validated | Y. Altera Board Name Arria 10 GX FPGA development kit |
| Industry standard compliance testing performed | N |
| If No, is it planned? | N |
| Interoperability | |
| IP has undergone interoperability testing | Y |
| Interoperability reports available | N |
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