10GbE TCP Offloading EngineIP core (TOE10G-IP)

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireline

Evaluation Method: Source Code

Technology: Interface Protocols: Ethernet

Arria Series: Intel® Arria® 10 SoC

Segments: 

Supported Device Family: 

Solution Type: 

Overview

10GbE TCP Offloading Engine(TOE10G-IP) IPcore is the epochal solution implemented without CPU. Usually TCP processing is complicated and needs an expensive high-end CPU. Because TOE10G-IPcore automatically takes over all functions of TCP/IP protocol which needs high-speed operation by hardware logic only. This IP product includes reference design for Intel® FPGA. It helps you to reduce development time.DesignGateway provide demo file for Intel FPGA boards. You can evaluate TOE10G-IPcore on real board before purchasing. For more information, visit http://www.dgway.com/TOE10G-IP_A_E.html

Features

  • 10GbE TCP/IP Stack Implementation By All HW Logic, Without CPU
  • Support both Server and Client mode (Passive/Active open and close)
  • Support Multi-session (8 Sessions Reference design is available)
  • 4
  • Rerference design is included in IP core license

Device Utilization and Performance

Intel Arria® 10 SX (10AS066N3F40E2SGE2) Fmax=156.25MHz, ALMs=2,411, Block Memory bit=1,179,648

Getting Started

1st Step: Download free evaluation sof file from DesignGateway official website / 2nd Step: Adapter board is provided from DesignGateway /3rd Step: Evaluate the IP core performance /4th Step: Purchasing IP core /For more information, visit http://www.dgway.com/TOE10G-IP_A_E.html

IP Quality Metrics

Basic
Year IP was first released2016
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Any additional customer deliverables provided with IP
Reference Design
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportN
Source language
VHDL
Testbench languageVHDL
Software drivers providedN
Driver OS supportN/A
Implementation
User InterfaceOther: Customized
IP-XACT Metadata includedN
Verification
Simulators supportedModelSim Altera Edition
Hardware validated Y. Altera Board Name Arria 10 SX SoC
Industry standard compliance testing performed
N
If No, is it planned?N
Interoperability
IP has undergone interoperability testing
Y
Interoperability reports available  N

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