VSC-1 Video Scaler with Shrink and Zoom Support

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Consumer, Industrial, Medical, Military, Test & Measurement

Evaluation Method: OpenCore Plus

Technology: DSP: Video and Image Processing

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

Stratix Series: Stratix® IV, Stratix® V

Segments: 

Supported Device Family: 

Solution Type: 

Overview

The VSC-1 is a high quality polyphase scaler which has been optimized for video and graphics applications. The scaler may be used in conjunction with the VPC-1 Video Processor and Deinterlacer IP core or with any other customer or third party IP. Support for both shrink and zoom modes allows full screen display of any video or graphics source as well as arbitrary resizing for PIP applications. Dynamically loadable coefficients provide maximum flexibility to optimize for different source types and to enable effects such as image sharpening. In addition, the core includes a number of Verilog parameters that allow it to be tailored at build time to satisfy specific requirements. Flexibility, robust design and rigorous testing combine to make the VSC-1 ideal for both consumer electronic and broadcast applications.

Features

  • High quality polyphase scaler optimized for video and graphics applications
  • Separate horizontal and vertical scalers
  • Correct filtering minimizes artifacts at all scale factors
  • Verilog build-time parameters for easy customization of key attributes including number of taps, number of phases and precision
  • Use standalone or in conjunction with VPC-1 Video Processor and Deinterlacer IP core

Device Utilization and Performance

1.7K ALMs, 409K bits, 20 DSPs (Cyclone® V)Fmax = 150 MHz(7x9 tap configuration)

Getting Started

Evaluation can be performed using pre-built bitstreams for standard Intel® FPGA dev kits or a time-limited trial of the actual IP

IP Quality Metrics

Basic
Year IP was first released2012
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Any additional customer deliverables provided with IP
Reference design targeted to standard Altera FPGA dev kit
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog
Testbench languageVerilog
Software drivers providedY
Driver OS supportC/C++ support functions
Implementation
User InterfaceAXI; Avalon-MM; Other: Generic bus
IP-XACT Metadata includedN
Verification
Simulators supportedQuartus II Simulator, ModelSim
Hardware validated Y. Altera Board Name Cyclone V GT FPGA Development Board
Industry standard compliance testing performed
Y
If yes, which test(s)?HQV 2.0 Benchmark
If yes, on which Altera device(s)?Cyclone V GT
If Yes, date performed
01/26/2016
Interoperability
IP has undergone interoperability testing
N
Interoperability reports available  N

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