VPC-5 Adaptive Detail Enhancer

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Consumer, Industrial, Medical, Military, Test & Measurement

Evaluation Method: OpenCore Plus

Technology: DSP: Video and Image Processing

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

Stratix Series: Stratix® IV, Stratix® V

Segments: 

Supported Device Family: 

Solution Type: 

Overview

The VPC-5 is a 2D adaptive detail enhancer which selectively enhances the appearance of edges and textures without enhancing the appearance of noise. Separate controls are provided for both edge and texture enhancement as well as for the amount of enhancement to be applied in each dimension. A programmable threshold for discriminating textures from noise is also provided. Careful algorithm design and piecewise linear control ensure a well behaved response without large changes at the output in response to small changes at the input. Programmable overshoot clamping is provided to limit the amount of overshoot associated with enhancement. The VPC-5 Adaptive Detail Enhancer can be combined with the VPC-3 Mosquito/Block Noise Reducer to provide a complete suite of enhancement and noise reduction tools.

Features

  • Selectively enhances sharpness of edges and textures
  • Separate controls provided for edge and texture enhancement
  • Enhances edges and textures without amplifying noise
  • Enhancement applied in both horizontal and vertical dimensions with separate level controls provided
  • Programmable overshoot clamping control

Device Utilization and Performance

960 ALMs, 57K bits, 6 DSPs (Cyclone® V)Fmax = 150 MHz

Getting Started

Evaluation can be performed using pre-built bitstreams for standard Intel® FPGA dev kits or a time-limited trial of the actual IP

IP Quality Metrics

Basic
Year IP was first released2014
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Any additional customer deliverables provided with IP
Reference design targeted to standard Altera FPGA dev kit
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog
Testbench languageVerilog
Software drivers providedY
Driver OS supportC/C++ support functions
Implementation
User InterfaceAXI; Avalon-MM; Other: Generic bus
IP-XACT Metadata includedN
Verification
Simulators supportedQuartus II Simulator, ModelSim
Hardware validated Y. Altera Board Name Cyclone V GT FPGA Development Board
Industry standard compliance testing performed
Y
If yes, which test(s)?HQV 2.0 Benchmark
If yes, on which Altera device(s)?Cyclone V GT
If Yes, date performed
01/26/2016
Interoperability
IP has undergone interoperability testing
N
Interoperability reports available  N

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