VPC-5 Adaptive Detail Enhancer
Block Diagram
Overview
The VPC-5 is a 2D adaptive detail enhancer which selectively enhances the appearance of edges and textures without enhancing the appearance of noise. Separate controls are provided for both edge and texture enhancement as well as for the amount of enhancement to be applied in each dimension. A programmable threshold for discriminating textures from noise is also provided. Careful algorithm design and piecewise linear control ensure a well behaved response without large changes at the output in response to small changes at the input. Programmable overshoot clamping is provided to limit the amount of overshoot associated with enhancement. The VPC-5 Adaptive Detail Enhancer can be combined with the VPC-3 Mosquito/Block Noise Reducer to provide a complete suite of enhancement and noise reduction tools.
Features
- Selectively enhances sharpness of edges and textures
- Separate controls provided for edge and texture enhancement
- Enhances edges and textures without amplifying noise
- Enhancement applied in both horizontal and vertical dimensions with separate level controls provided
- Programmable overshoot clamping control
IP Quality Metrics
| Basic | |
|---|---|
| Year IP was first released | 2014 |
| Latest version of Quartus supported | 15.1 |
| Altera Customer Use | |
| IP has been successfully implemented in production with at least one customer | Y |
| Deliverables | |
Customer deliverables include the following:
|
Y |
| Any additional customer deliverables provided with IP | Reference design targeted to standard Altera FPGA dev kit |
| Parameterization GUI allowing end user to configure IP | Y |
| IP core is enabled for OpenCore Plus Support | Y |
| Source language | Verilog |
| Testbench language | Verilog |
| Software drivers provided | Y |
| Driver OS support | C/C++ support functions |
| Implementation | |
| User Interface | AXI; Avalon-MM; Other: Generic bus |
| IP-XACT Metadata included | N |
| Verification | |
| Simulators supported | Quartus II Simulator, ModelSim |
| Hardware validated | Y. Altera Board Name Cyclone V GT FPGA Development Board |
| Industry standard compliance testing performed | Y |
| If yes, which test(s)? | HQV 2.0 Benchmark |
| If yes, on which Altera device(s)? | Cyclone V GT |
| If Yes, date performed | 01/26/2016 |
| Interoperability | |
| IP has undergone interoperability testing | N |
| Interoperability reports available | N |
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