VPC-3 Mosquito/Block Noise Reducer

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Consumer, Industrial, Medical, Military, Test & Measurement

Evaluation Method: OpenCore Plus

Technology: DSP: Video and Image Processing

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

Stratix Series: Stratix® IV, Stratix® V

Segments: 

Supported Device Family: 

Solution Type: 

Overview

The VPC-3 provides noise reduction functionality which targets both mosquito noise and block noise associated with digital compression. Mosquito noise reduction reduces noise which often occurs near edges, due to quantization of DCT coefficients. Block artifact reduction detects and adaptively softens block boundaries frequently visible in regions of low variability. In either case, an advanced algorithm ensures that noise reduction is achieved with minimal undesired loss of detail. Automatic detection of block boundaries means that no prior knowledge of video format or block alignment is required. When combined with the Gaussian noise reduction feature of the VPC-1 Deinterlacer IP core, a complete noise reduction suite is provided to address most types of noise.

Features

  • Reduces mosquito noise associated with digital compression
  • Detects and adaptively softens block boundaries frequently visible in regions of low variability
  • Separately controllable levels for both Mosquito Noise Reduction and Block Artifact Reduction
  • Minimizes undesired loss of detail
  • Compatible with both progressive and interlaced sources

Device Utilization and Performance

2.8K ALMs, 235K bits, 9 DSPs (Cyclone® V)Fmax = 150 MHz

Getting Started

Evaluation can be performed using pre-built bitstreams for standard Intel® FPGA dev kits or a time-limited trial of the actual IP

IP Quality Metrics

Basic
Year IP was first released2014
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Any additional customer deliverables provided with IP
Reference design targeted to standard Altera FPGA dev kit
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog
Testbench languageVerilog
Software drivers providedY
Driver OS supportC/C++ support functions
Implementation
User InterfaceAXI; Avalon-MM; Other: Generic bus
IP-XACT Metadata includedN
Verification
Simulators supportedQuartus II Simulator, ModelSim
Hardware validated Y. Altera Board Name Cyclone V GT FPGA Development Board
Industry standard compliance testing performed
Y
If yes, which test(s)?HQV 2.0 Benchmark
If yes, on which Altera device(s)?Cyclone V GT
If Yes, date performed
01/26/2016
Interoperability
IP has undergone interoperability testing
N
Interoperability reports available  N

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