VPC-1 Video Processor and Deinterlacer with Line-Doubled Output
Block Diagram

Overview
The VPC-1 is a high quality motion adaptive deinterlacer and video processor with line-doubled output. Additional functions include motion adaptive noise reduction, low angle directional interpolation and film cadence detection (supports multiple cadences including 3:2, 2:2 and others). When combined with Crucial IP's VSC-1 scaler core, the VPC-1 can be used to provide complete up/down/cross conversion. Years of experience in developing video processing algorithms have contributed to the outstanding performance of the VPC-1 amongst motion adaptive class solutions. The full feature set, robust performance and extremely efficient implementation make the VPC-1 ideal for both consumer electronic and broadcast applications.
IP Quality Metrics
Basic | |
---|---|
Year IP was first released | 2012 |
Latest version of Quartus supported | 15.1 |
Altera Customer Use | |
IP has been successfully implemented in production with at least one customer | Y |
Deliverables | |
Customer deliverables include the following:
|
Y |
Any additional customer deliverables provided with IP | Reference design targeted to standard Altera FPGA dev kit |
Parameterization GUI allowing end user to configure IP | Y |
IP core is enabled for OpenCore Plus Support | Y |
Source language | Verilog |
Testbench language | Verilog |
Software drivers provided | Y |
Driver OS support | C/C++ support functions |
Implementation | |
User Interface | AXI; Avalon-MM; Other: Generic bus |
IP-XACT Metadata included | N |
Verification | |
Simulators supported | Quartus II Simulator, ModelSim |
Hardware validated | Y. Altera Board Name Cyclone V GT FPGA Development Board |
Industry standard compliance testing performed | Y |
If yes, which test(s)? | HQV 2.0 Benchmark |
If yes, on which Altera device(s)? | Cyclone V GT |
If Yes, date performed | 01/26/2016 |
Interoperability | |
IP has undergone interoperability testing | N |
Interoperability reports available | N |
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