Wideband DDC Digital Down Converter

Block Diagram

Solution Type: IP Core

End Market: Broadcast, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore Plus

Technology: DSP: Error Detection and Correction

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

Stratix Series: Stratix® IV, Stratix® V


The Creonic Wideband Digital Down Converter (DDC) digitally converts the input signal at IF frequency down to baseband by multiplying input samples with sine/cosine waves generated by numerical controlled oscillators (NCO). Down converted samples are then decimated by a factor ranging from 2 to 2048 with multiplying step of 2. A CIC and 4 stages of half band filters are integrated within the decimator. The core accepts a real signal at input and provides complex I/Q baseband data at the output. The parallel architecture of the core allows for an input throughput up to 2.4 Gsps, data symbol rate up to 540 Msymb/s, making it a perfect fit for ultra high throughput applications such as wideband DVB-S2X communication.


  • High throughput wideband digital down converter
  • Up to 600 MHz signal bandwidth
  • Tunable IF frequency
  • Integrated decimator and filters
  • Contains Numerical Controlled Oscillators, IF mixers, decimator, and halfband filters.

Device Utilization and Performance

High input throughput of up to 2.4 Gsps Supported signal bandwidth of up to 600 MHz Tunable IF frequency from 10 to 700 MHz with a precision of at least 2 Hz Spurious-free dynamic range (SFDR) of at least 83 dB, filter’s passband ripple less than 0.05 dB

Getting Started

Contact us at sales@creonic.com if you need more information about our IP Cores

IP Quality Metrics

Year IP was first released2016
Latest version of Quartus supported17.0
Altera Customer Use
IP has been successfully implemented in production with at least one customerY

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Any additional customer deliverables provided with IP
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportY
Source language
Testbench languageVHDL
Software drivers providedN
Driver OS supportn/a
User InterfaceAXI
IP-XACT Metadata includedN
Simulators supportedModelSim, RivieraPRO
Hardware validated N. Altera Board Name NULL
Industry standard compliance testing performed
If No, is it planned?Y
IP has undergone interoperability testing
Interoperability reports available  N

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