MMSE MIMO
Block Diagram

Overview
MIMO (Multiple Input Multiple Output) techniques are be- ing used more and more in recent and upcoming stan- dards since they drastically outperform traditional SISO (Single Input Single Output) techniques in terms of max- imum throughput and range. This gain results from an increased spectral efficiency, lowering the overall system costs. A Minimum Mean Square Error (MMSE) MIMO detec- tor is an integral part of a MIMO receiver. The Creonic MMSE detector offers high throughputs even on low-cost FPGAs and convinces with a low implementation com- plexity at the same time. Its flexibility at design-time and run-time makes it the ideal fit for all kinds of MIMO appli- cations.
IP Quality Metrics
Basic | |
---|---|
Year IP was first released | 2013 |
Latest version of Quartus supported | 15.1 |
Altera Customer Use | |
IP has been successfully implemented in production with at least one customer | Y |
Deliverables | |
Customer deliverables include the following:
|
Y |
Any additional customer deliverables provided with IP | no |
Parameterization GUI allowing end user to configure IP | N |
IP core is enabled for OpenCore Plus Support | Y |
Source language | VHDL |
Testbench language | VHDL |
Software drivers provided | N |
Driver OS support | n/a |
Implementation | |
User Interface | AXI |
IP-XACT Metadata included | N |
Verification | |
Simulators supported | ModelSim, RivieraPRO |
Hardware validated | N. Altera Board Name NULL |
Industry standard compliance testing performed | N |
If No, is it planned? | Y |
Interoperability | |
IP has undergone interoperability testing | N |
Interoperability reports available | N |
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