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MMSE MIMO

Block Diagram

Solution Type: IP Core

End Market: Broadcast, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore Plus

Technology: DSP: Error Detection and Correction

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

Stratix Series: Stratix® IV, Stratix® V

Overview

MIMO (Multiple Input Multiple Output) techniques are be- ing used more and more in recent and upcoming stan- dards since they drastically outperform traditional SISO (Single Input Single Output) techniques in terms of max- imum throughput and range. This gain results from an increased spectral efficiency, lowering the overall system costs. A Minimum Mean Square Error (MMSE) MIMO detec- tor is an integral part of a MIMO receiver. The Creonic MMSE detector offers high throughputs even on low-cost FPGAs and convinces with a low implementation com- plexity at the same time. Its flexibility at design-time and run-time makes it the ideal fit for all kinds of MIMO appli- cations.

Features

Adaptable to differenttransmitter/receiver antennaconfigurations (e.g., 2x2, 4x2 or 4x4)
Support for different modulationschemes at run-time (e.g., QPSK,16-QAM, 64-QAM, 256-QAM)
QR decomposition included

Device Utilization and Performance

Receiver x Transmitter: 4x4 Modulation symbols per clock cycle: 0.4 Throughput @ 100 MHz (Mbit/s) QPSK 16-QAM 64-QAM 256-QAM (M=2) (M=4) (M=6) (M=8) 80 160 240 320

Getting Started

Please contact the Creonic Sales Team!

IP Quality Metrics

Basic
Year IP was first released	2013
Latest version of Quartus supported	15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customer	Y
Deliverables
Customer deliverables include the following: Design file (encrypted source code or post-synthesis netlist) Simulation model for ModelSim Altera edition Timing and/or layout constraints Testbench or design example Documentation with revision control Readme file	Y
Any additional customer deliverables provided with IP	no
Parameterization GUI allowing end user to configure IP	N
IP core is enabled for OpenCore Plus Support	Y
Source language	VHDL
Testbench language	VHDL
Software drivers provided	N
Driver OS support	n/a
Implementation
User Interface	AXI
IP-XACT Metadata included	N
Verification
Simulators supported	ModelSim, RivieraPRO
Hardware validated	N. Altera Board Name NULL
Industry standard compliance testing performed	N
If No, is it planned?	Y
Interoperability
IP has undergone interoperability testing	N
Interoperability reports available	N

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