Cyclone Series:Intel® Cyclone® 10: Intel® Cyclone® 10 GX, Intel® Cyclone® 10 LP; Cyclone® IV, Cyclone® V, Cyclone® V SoC
MAX Series: Intel® MAX® 10, MAX® V
Stratix Series: Intel® Stratix® 10, Stratix® IV, Stratix® V
The Creonic AWGN Channel IP is a noise generator ca-pable of processing up to a maximum of 512 symbolsin parallel. The IP was developed with the aim of allow-ing the performance evaluation of a digital communica-tion system in the presence of Additive White GaussianNoise. The emphasis is on evaluating systems with lowbit error rates. Unlike a software-based AWGN gener-ator, which might take several hours and even days forthe stated purpose, a hardware-based AWGN generatorrequires significantly less time. Run-time is reduced byseveral orders of magnitude.
Support for up to 512 symbols inparallel at 245 MHz
Support for SNR (ES/N0) in the rangefrom -10 to 41dBwith steps of 0.1dB±~ 0.01dB
Synchronous design with one clock
Noise sequence periodicallygenerated at ~264≈2x1019samples
Based on Box-Muller algorithm
Device Utilization and Performance
Symbol rate of 125.44 Gsymb/s at 245 MHz.
Latency of 36.73nsat 245 MHz
IP has been successfully implemented in production with at least one customer
Customer deliverables include the following:
Design file (encrypted source code or post-synthesis netlist)
Simulation model for ModelSim Altera edition
Timing and/or layout constraints
Testbench or design example
Documentation with revision control
Parameterization GUI allowing end user to configure IP
IP core is enabled for OpenCore Plus Support
Software drivers provided
Driver OS support
IP-XACT Metadata included
N. Altera Board Name NULL
Industry standard compliance testing performed
If No, is it planned?
IP has undergone interoperability testing
Interoperability reports available
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