IEEE 802.15.3c LDPC Decoder

Block Diagram

Solution Type: IP Core

End Market: Broadcast, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore Plus

Technology: DSP: Error Detection and Correction

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

Stratix Series: Stratix® IV, Stratix® V


The IEEE 802.15 working group specifies standards targeting the wireless personal area network (WPAN). Task group 3 of the working group focuses on high data rates within WPAN. The task group 3c defined a new millimeter-wave-based alternative physical layer (PHY) for the IEEE 802.15.3-2003 standard. This standard (IEEE 802.15.3c-2009) operates at 60 GHz and offers data rates of multiple Gbit/s for applications such as high speed internet access or streaming content download. The task group adopted LDPC codes for these high data rate modes within the single carrier (SC) mode and the high speed interface (HSI) mode. The Creonic IEEE 802.15.3c LDPC Decoder IP supports all LDPC codes with a codeword size of 672 bits as defined by the standard.


    Device Utilization and Performance

    -support for all short LDPC codes (672 bits, code rates 1/2, 5/8, 3/4, 7/8)

    Getting Started

    Please contact the Creonic Sales Team!

    IP Quality Metrics

    Year IP was first released2013
    Latest version of Quartus supported15.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Any additional customer deliverables provided with IP
    Parameterization GUI allowing end user to configure IPN
    IP core is enabled for OpenCore Plus SupportY
    Source language
    Testbench languageVHDL
    Software drivers providedN
    Driver OS supportn/a
    User InterfaceOther: proprietary
    IP-XACT Metadata includedN
    Simulators supportedModelSim, RivieraPRO
    Hardware validated N. Altera Board Name DE1, DE2
    Industry standard compliance testing performed
    If No, is it planned?Y
    IP has undergone interoperability testing
    Interoperability reports available  N

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