IEEE 802.11ad WiGig LDPC Decoder

Block Diagram

Solution Type: IP Core

End Market: Broadcast, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore Plus

Technology: DSP: Error Detection and Correction

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

Stratix Series: Stratix® IV, Stratix® V

Overview

The WiGig standard (IEEE 802.11ad) delivers data rates of up to 7 Gbit/s and hence outperforms the current IEEE 802.11n standard by more than 10x. It uses the 60 GHz band to enable short range communication and interoper- ability between a broad set of applications and platforms. The Creonic WiGig LDPC decoder is designed in par- ticular to deliver highest throughputs in the multi-gigabit domain with a small footprint. At the same time it provides outstanding error correction performance, resulting in a low energy consumption and increasing range of wire- less transmission. Its unique pipeline architecture can be customized at design-time to deliver best performance on any target technology. Insertion, removal and balancing of pipeline stages within the IP core is flexible and allows for optimization of required routing resources, path delays between pipeline stages, throughput, and footprint at the same time.

Features

  • Compliant with IEEE 802.11ad(WiGig)
  • Support for 672 bits code words
  • Support for all LDPC code rates(1/2, 5/8, 3/4, and 13/16)

Device Utilization and Performance

-coded throughput of 2.1 Gbit at 10 iterations (250 MHz) -Bit Error Rate 10-6 with code rate ¾ at -(EB/N0)= 4.2 dB (BPSK) -(EB/N0)= 7.5 dB (16 QAM)

Getting Started

Please contact the Creonic Sales Team!

IP Quality Metrics

Basic
Year IP was first released2016
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Any additional customer deliverables provided with IP
no
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportY
Source language
VHDL
Testbench languageVHDL
Software drivers providedN
Driver OS supportn/a
Implementation
User InterfaceOther: proprietary
IP-XACT Metadata includedN
Verification
Simulators supportedModelSim, RivieraPRO
Hardware validated N. Altera Board Name NULL
Industry standard compliance testing performed
N
If No, is it planned?Y
Interoperability
IP has undergone interoperability testing
N
Interoperability reports available  N

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