From Creonic

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Documentation

DVB-S2X Modulator

Overview

Features

Device Utilization

Getting Started

IP Quality Metrics

Block Diagram

Solution Type: IP Core

End Market: Broadcast, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore Plus

Technology: DSP

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

Stratix Series: Stratix® IV, Stratix® V

Segments: 

Supported Device Family: 

Solution Type: 

Overview

The Creonic DVB-S2X high performance modulator performs all tasks of an inner transmitter. The modulator expects BBFrames after mode adaptation as input and performs stream adaptation, FEC encoding, mapping, PL framing and modulation. In addition the core can perform baseband interpolation and output gain adjustment. The output of the core is designed to be followed by a DAC and RF front end.

Features

    Device Utilization and Performance

    -clock frequency up to 200 MHz - Max. symbol rate: 200 MSymb/s normal frames: 64800 bits short frames: 16200 bits

    Getting Started

    Please contact Creonic Sales Team!

    IP Quality Metrics

    Basic
    Year IP was first released2015
    Latest version of Quartus supported15.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerN
    Deliverables

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    		 N
    Any additional customer deliverables provided with IP
    		no
    Parameterization GUI allowing end user to configure IPN
    IP core is enabled for OpenCore Plus SupportY
    Source language
    		VHDL
    Testbench languageVHDL
    Software drivers providedN
    Driver OS supportn/a
    Implementation
    User InterfaceAXI
    IP-XACT Metadata includedN
    Verification
    Simulators supportedModelSim, RivieraPRO
    Hardware validated N. Altera Board Name SLS Cyclone III based CoreCommander, SLS Embedded System Development Kit (ESDK)
    Industry standard compliance testing performed
    		N
    If No, is it planned?Y
    Interoperability
    IP has undergone interoperability testing
    		N
    Interoperability reports available  N

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