Block Diagram

Solution Type: IP Core

End Market: Broadcast, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore Plus

Technology: DSP

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

Stratix Series: Stratix® IV, Stratix® V


The Creonic DVB-S2X decoder is a silicon-proven, scalable solution that allows for symbol rates of up to 100 MSymb/s on state-of-the-art FPGAs.


  • Compliant with DVB-S2 and DVB-S2X
  • Support for decoding of BBFRAMEs
  • Support for ACM, CCM, and VCM
  • Support for very low SNR modes(VLSNR) with SNRs below -9 dB
  • Support for short, medium, andnormal frames (16 200 bits, 32 400and 64 800 bits)

Device Utilization and Performance

-signal-to-noise ratio ranges from -9.6 to 19.8 dB -throughput of up to 100 MSymb/s even for 256-APSK

Getting Started

Please contact Creonic Sales team!

IP Quality Metrics

Year IP was first released2014
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerN

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Any additional customer deliverables provided with IP
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportY
Source language
Testbench languageVHDL
Software drivers providedN
Driver OS supportn/a
User InterfaceAXI
IP-XACT Metadata includedN
Simulators supportedModelSim, RivieraPRO
Hardware validated N. Altera Board Name NULL
Industry standard compliance testing performed
If No, is it planned?Y
IP has undergone interoperability testing
Interoperability reports available  N

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