DVB-S2X Demodulator

Block Diagram

Solution Type: IP Core

End Market: Broadcast, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore Plus

Technology: DSP

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

Stratix Series: Stratix® IV, Stratix® V

Segments: 

Supported Device Family: 

Solution Type: 

Overview

The Creonic DVB-S2X high performance demodulator performs all tasks of an inner receiver. The demodulator expects the quantized, complex baseband samples from an analog-digital-converter (ADC) and recovers timing, frequency and phase of the complex mapped symbols. In addition the core handles PL frame recovery and PL de-framing. The output of the demodulator perfectly fits the Creonic DVB-S2X forward error correction IP core that implements LDPC and BCH decoding.

Features

  • -compliant with DVB-S2 and DVB-S2X
  • -support ACM, CCM and VCM modes
  • -support for short and long blocks (16200 bits and 64800 bits)
  • -support for QPSK to 256-APSK, VLSNR modes on request
  • -output of XFECFRAMEs for further processing by the Creonic FEC decoder

Device Utilization and Performance

-symbol rates -clock frequency (MHz) 220 -maximum symbol rate (Msymb/s) 100 -normal Frames (64,800 Bits) -short Frames (16,200 Bits) VLSNR Frames

Getting Started

Please contact Creonic Sales Team!

IP Quality Metrics

Basic
Year IP was first released2014
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerN
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
N
Any additional customer deliverables provided with IP
no
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportY
Source language
VHDL
Testbench languageVHDL
Software drivers providedN
Driver OS supportn/a
Implementation
User InterfaceAXI
IP-XACT Metadata includedN
Verification
Simulators supportedModelSim, RivieraPRO
Hardware validated N. Altera Board Name SLS Cyclone III based CoreCommander, SLS Embedded System Development Kit (ESDK)
Industry standard compliance testing performed
N
If No, is it planned?Y
Interoperability
IP has undergone interoperability testing
N
Interoperability reports available  N

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