DVB-S2 LDPC/ BCH Decoder
Block Diagram
Overview
DVB-S2 (Digital Video Broadcast - Satellite 2nd Generation) is an ETSI standard of the second generation for digital data transmission via satellites. It was published in 2005, being the first standard of the second generation DVB standards (DVB-S2/-T2/-C2). Because of its capacity-approaching forward error correction, today DVB-S2 is the de-facto standard in satellite communication and other applications. The Creonic DVB-S2 IP core integrates the forward error correction as defined by the standard (including LDPC and BCH decoder).
IP Quality Metrics
| Basic | |
|---|---|
| Year IP was first released | 2012 |
| Latest version of Quartus supported | 15.1 |
| Altera Customer Use | |
| IP has been successfully implemented in production with at least one customer | Y |
| Deliverables | |
Customer deliverables include the following:
|
Y |
| Any additional customer deliverables provided with IP | no |
| Parameterization GUI allowing end user to configure IP | N |
| IP core is enabled for OpenCore Plus Support | Y |
| Source language | VHDL |
| Testbench language | VHDL |
| Software drivers provided | N |
| Driver OS support | n/a |
| Implementation | |
| User Interface | AXI |
| IP-XACT Metadata included | N |
| Verification | |
| Simulators supported | ModelSim, RivieraPRO |
| Hardware validated | N. Altera Board Name DE1, DE2 |
| Industry standard compliance testing performed | N |
| If No, is it planned? | Y |
| Interoperability | |
| IP has undergone interoperability testing | N |
| Interoperability reports available | N |
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