DVB-S2 Demodulator

Block Diagram

Solution Type: IP Core

End Market: Broadcast, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore Plus

Technology: DSP: Error Detection and Correction

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

Stratix Series: Stratix® IV, Stratix® V

Segments: 

Supported Device Family: 

Solution Type: 

Overview

DVB-S2 (Digital Video Broadcast - Satellite 2nd Gen- eration) is an ETSI standard of the second generation for digital data transmission via satellites. It was pub- lished in 2005, being the first standard of the second generation DVB standards (DVB-S2/-T2/-C2). Because of its capacity-approaching forward error correction, to- day DVB-S2 is the de-facto standard in satellite commu- nication and other applications. The Creonic DVB-S2 high performance demodulator performs all tasks of an inner receiver. The demodula- tor expects the quantized, complex baseband samples from an analog-digital-converter (ADC) and recovers tim- ing, frequency and phase of the complex mapped sym- bols. In addition the core handles PL frame recovery and PL de-framing. The output of the demodulator perfectly fits the Creonic DVB-S2 forward error correction IP core that implements LDPC and BCH decoding.

Features

  • -compliant with ETSI EN 302 307 V1.2.1 (2009-08) (DVB-S2)

Device Utilization and Performance

Throughput: clock frequency about 150 MHz -minimum symbol rate: 6.25 MSymb/s -maximum symbol rate: 50 MSymb/s Communication Performance: Normal Frames: 64000 Bits Short Frames: 16200 Bits

Getting Started

Please contact the Creonic Sales Team!

IP Quality Metrics

Basic
Year IP was first released2014
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Any additional customer deliverables provided with IP
no
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportY
Source language
VHDL
Testbench languageVHDL
Software drivers providedN
Driver OS supportn/a
Implementation
User InterfaceAXI
IP-XACT Metadata includedN
Verification
Simulators supportedModelSim, RivieraPRO
Hardware validated N. Altera Board Name Arria V GX, Stratix V GX, Cyclone V SX SoC, Arria V ST SoC, Stratix IV GX
Industry standard compliance testing performed
N
If No, is it planned?Y
Interoperability
IP has undergone interoperability testing
N
Interoperability reports available  N

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