DVB-RCS2 Modulator

Block Diagram

Solution Type: IP Core

End Market: Broadcast, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore Plus

Technology: DSP: Error Detection and Correction

eASIC™ Series: Intel® eASIC™ N2X, Intel® eASIC™ N2XT, Intel® eASIC™ N3X, Intel® eASIC™ N3XS

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Intel® Cyclone® 10: Intel® Cyclone® 10 GX, Intel® Cyclone® 10 LP; Cyclone® IV, Cyclone® V, Cyclone® V SoC

MAX Series: MAX® V

Stratix Series: Intel® Stratix® 10, Stratix® IV, Stratix® V

Overview

The Creonic DVB-RCS2 high performance modulatorperforms all tasks of a Modulator. The modulator ex-pects PDU frames as input and performs energy disper-sal, CRC encoding, turbo encoding, mapping, framingand modulation. In addition, the core performs basebandfiltering and output gain adjustment. The output of thecore is designed to be followed by a DAC.

Features

  • •Compliant with DVB-RCS2 •Support for Pi/2-BPSK, QPSK,8-PSK, and 16-QAM •Support for all linear burst modulationwaveforms specified in Annex A •Output

Device Utilization and Performance

DVB-RCS2 Modulator Clock frequency 200 MHz Maximum Symbol rate 40 MSymb/s

Getting Started

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IP Quality Metrics

Basic
Year IP was first released2018
Latest version of Quartus supported18.0
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Any additional customer deliverables provided with IP
n/a
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportN
Source language
VHDL
Testbench languageVHDL
Software drivers providedN
Driver OS supportn/a
Implementation
User InterfaceAXI
IP-XACT Metadata includedN
Verification
Simulators supportedModelSim, Riviera PRO
Hardware validated N. Altera Board Name Customer HW
Industry standard compliance testing performed
N
If No, is it planned?Y
Interoperability
IP has undergone interoperability testing
N
Interoperability reports available  N

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