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DVB-C2 LDPC/ BCH Decoder

Block Diagram

Solution Type: IP Core

End Market: Broadcast, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore Plus

Technology: DSP: Error Detection and Correction

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

Stratix Series: Stratix® IV, Stratix® V

Segments:

Supported Device Family:

Solution Type:

Overview

DVB-C2 (Digital Video Broadcast - Cable 2nd Genera- tion) is an ETSI standard of the second generation for dig- ital data transmission via cable networks. It complements the existing standards DVB-S2 and DVB-T2 for satel- lite and terrestrial communication and offers a capacity- approaching coding scheme. The Creonic DVB-C2 IP core integrates the forward er- ror correction as defined by the standard (including LDPC and BCH decoder).

Features

-compliant with ETSI 302 769 V1.2.1 (2011-04) (DVB-C2)
-support for short and long blocks (16,200 bits and 64,800 bits)
-support for decoding of L1 signalling part 2 data
-support for all interleaving schemes of all modulation schemes
-support for all LDPC and BCH codes as defined by the standard

Device Utilization and Performance

-support for all modulation schemes (16-QAM, 64-QAM, 256-QAM, 1024-QAM, 4096-QAM)

Getting Started

Please contact the Creonic Sales team!

IP Quality Metrics

Basic
Year IP was first released	2013
Latest version of Quartus supported	15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customer	Y
Deliverables
Customer deliverables include the following: Design file (encrypted source code or post-synthesis netlist) Simulation model for ModelSim Altera edition Timing and/or layout constraints Testbench or design example Documentation with revision control Readme file	Y
Any additional customer deliverables provided with IP	no
Parameterization GUI allowing end user to configure IP	N
IP core is enabled for OpenCore Plus Support	Y
Source language	VHDL
Testbench language	VHDL
Software drivers provided	N
Driver OS support	n/a
Implementation
User Interface	Other: proprietary
IP-XACT Metadata included	N
Verification
Simulators supported	ModelSim, RivieraPRO
Hardware validated	N. Altera Board Name DE1, DE2
Industry standard compliance testing performed	N
If No, is it planned?	Y
Interoperability
IP has undergone interoperability testing	N
Interoperability reports available	N

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