Block Diagram

Solution Type: IP Core

End Market: Broadcast, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore Plus

Technology: DSP: Error Detection and Correction

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

Stratix Series: Stratix® IV, Stratix® V


Data Over Cable Service Interface Specification (DOCSIS) is an international telecommunications standard that permits the addition of high-bandwidth data transfer to an existing cable TV (CATV) system. It is employed by many cable television operators to provide Internet access over their existing hybrid fiber-coaxial infrastructure. The Downstream (DS) NCP (Next Codeword Pointer) Decoder decodes NCP frames and there fore allows to convey plenty of information on the OFDM structure.


  • Parity deinterleaver, LDPC decoder,shortening unit, and BCH decoderincluded
  • Support for all block sizes withshortening (3 to 1779 bytes payload)
  • Support for data rates of more than2.3 Gbit/s
  • Soft-Decision demapper,derandomizer, deinterleaver,depuncturing unit, and LDPC decoderincluded
  • Support for 16-QAM modulation & Support for 4k and 8k FFT size

Device Utilization and Performance

-support for 16 QAM modulation -support for 4k and 8k FFT size -support for QPSK, 16 QAM and 64 QAM modulation

Getting Started

Please contact Creonic Sales Team!

IP Quality Metrics

Year IP was first released2015
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Any additional customer deliverables provided with IP
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportY
Source language
Testbench languageVHDL
Software drivers providedN
Driver OS supportn/a
User InterfaceOther: proprietary
IP-XACT Metadata includedN
Simulators supportedModelSim, RivieraPRO
Hardware validated N. Altera Board Name NULL
Industry standard compliance testing performed
If No, is it planned?Y
IP has undergone interoperability testing
Interoperability reports available  N

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