CCSDS SCCC Turbo Encoder + Decoder
Block Diagram

Overview
The recommended CCSDS 131.2-B-1 standard in-troduces a Serial Concatenated Convolutional Code(SCCC). Main goal of this code is to allow an efficientuse of available bandwidth, by allowing to select from 27valid configurations with a wide range of constellations,block lengths and code rates.The outstanding error correction performance of theSCCC code in combination with the high data ratesmakes this IP core the ideal fit for further applicationswhere high throughput and high spectral efficiency is keyfor operation.
Device Utilization and Performance
Coded throughput of up to 1.25 Gbit/s at 200 MHz and10 iterations Symbol rates of up to 372 MSymbols/s at 200 MHz ES/N0at 20 iterations and block error rate of10−4:–1.7dB(QPSK, 16,200 bits, code rate 0.52)–4.01dB(8-PSK, 24,300 bits, code rate 0.46)–8.28dB(16-APSK, 32,400 bits, code rate 0.59)–11.56dB(32-APSK, 40,500 bits, code rate 0.64)–14.83dB(64-APSK, 48,600 bits, code rate 0.69)
IP Quality Metrics
Basic | |
---|---|
Year IP was first released | 2019 |
Latest version of Quartus supported | 18.0 |
Altera Customer Use | |
IP has been successfully implemented in production with at least one customer | N |
Deliverables | |
Customer deliverables include the following:
|
N |
Parameterization GUI allowing end user to configure IP | N |
IP core is enabled for OpenCore Plus Support | Y |
Source language | VHDL |
Testbench language | VHDL |
Software drivers provided | N |
Driver OS support | n/a |
Implementation | |
User Interface | Other: Proprietary |
IP-XACT Metadata included | N |
Verification | |
Simulators supported | ModelSim, Riviera Pro |
Hardware validated | N. Altera Board Name NULL |
Industry standard compliance testing performed | N |
If No, is it planned? | Y |
Interoperability | |
IP has undergone interoperability testing | N |
Interoperability reports available | N |
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