CCSDS AR4JA LDPC Encoder & Decoder
Block Diagram

Overview
The Creonic CCSDS AR4JA LDPC IP supports the LDPC coding schemes as defined by the CCSDS standard. The LDPC codes with rates 1/2, 2/3 and 4/5, block lengths 1024, 4096 and 16384 are specially designed for deep-space missions, but the excellent error correction performance makes it the ideal fit for further applications with the highest demands on forward error correction
IP Quality Metrics
Basic | |
---|---|
Year IP was first released | 2016 |
Latest version of Quartus supported | 15.1 |
Altera Customer Use | |
IP has been successfully implemented in production with at least one customer | N |
Deliverables | |
Customer deliverables include the following:
|
N |
Any additional customer deliverables provided with IP | no |
Parameterization GUI allowing end user to configure IP | N |
IP core is enabled for OpenCore Plus Support | Y |
Source language | VHDL |
Testbench language | VHDL |
Software drivers provided | N |
Driver OS support | n/a |
Implementation | |
User Interface | Other: proprietary |
IP-XACT Metadata included | N |
Verification | |
Simulators supported | ModelSim, RivieraPRO |
Hardware validated | N. Altera Board Name NULL |
Industry standard compliance testing performed | N |
If No, is it planned? | Y |
Interoperability | |
IP has undergone interoperability testing | N |
Interoperability reports available | N |
Design Solutions Network Members provide products and/or services that are sold or licensed by the Member and not Altera or its affiliates. Altera and its affiliates hereby disclaim any express or implied warranty of any kind including warranties of merchantability, noninfringement of intellectual property, or fitness for any particular purpose with respect to any such products and/or services.