From Creonic

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Documentation

CCSDS AR4JA LDPC Encoder & Decoder

Overview

Features

Device Utilization

Getting Started

IP Quality Metrics

Block Diagram

Solution Type: IP Core

End Market: Broadcast, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore Plus

Technology: DSP: Error Detection and Correction

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

Stratix Series: Stratix® IV, Stratix® V

Segments: 

Supported Device Family: 

Solution Type: 

Overview

The Creonic CCSDS AR4JA LDPC IP supports the LDPC coding schemes as defined by the CCSDS stan- dard. The LDPC codes with rates 1/2, 2/3 and 4/5, block lengths 1024, 4096 and 16384 are specially designed for deep-space missions, but the excellent error correction performance makes it the ideal fit for further applications with highest demands on forward error correction

Features

  • • Support for code rates 1/2, 2/3, and 4/5
  • • Uncoded block sizes of 1024, 4096, and 16384 bits
  • • Compliant with “TM Synchronization and Channel Coding, Recommended Standard, CCSDS 131.0-B-2, Blue Book, August 2011”

Device Utilization and Performance

• Encoder payload throughput of up to 100 Mbit/s at 200 MHz • Decoder payload throughput of up to more than 100 Mbit/s (30 iterations, 200 MHz)

Getting Started

Contract Creonic Sales Team for more information!

IP Quality Metrics

Basic
Year IP was first released2016
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerN
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
 N
Any additional customer deliverables provided with IP
no
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportY
Source language
VHDL
Testbench languageVHDL
Software drivers providedN
Driver OS supportn/a
Implementation
User InterfaceOther: proprietary
IP-XACT Metadata includedN
Verification
Simulators supportedModelSim, RivieraPRO
Hardware validated N. Altera Board Name NULL
Industry standard compliance testing performed
N
If No, is it planned?Y
Interoperability
IP has undergone interoperability testing
N
Interoperability reports available  N

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