5G NR LDPC Decoder

Block Diagram

Solution Type: IP Core

End Market: Broadcast, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore Plus

Technology: DSP: Error Detection and Correction

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

Stratix Series: Stratix® IV, Stratix® V


5G NR is the mobile broadband standard of the 5th gen-eration. A new rate compatible structure for LDPC codesare employed for channel coding to fulfill the broad appli-cations supported by the standard.Creonic’s 5G LDPC Decoder IP Core provides a per-fect solution for this new LDPC structure with high levelof flexibility while maintaining high throughput and low la-tency as required by the standard.


  • •Support for 3GPP Release 15 5GLDPC decoding•Support for base code rates from22/68 to 22/26 for basegraph 1•Support for base code rates from10/52 to 1

Device Utilization and Performance

•Throughput up to 574 Mbits/s. •Low-power and low-complexity design .•Block-to-block on-the-fly configuration. •AXI4-Stream handshaking interfaces for seamless in-tegration. •Design-time configuration of throughput for optimal re-source utilization. •Faster convergence due to layered LDPC decoder ar-chitecture. •Early stopping criterion for iterative LDPC decoder,saving a considerable amount of energy. •Collection of statistics (decoding success, iterationsneeded). •Available for ASIC and FPGAs

Getting Started

Please contact the Creonic Sales Team!

IP Quality Metrics

Year IP was first released2019
Latest version of Quartus supported18.0
Altera Customer Use
IP has been successfully implemented in production with at least one customerN

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportY
Source language
Testbench languageVHDL
Software drivers providedN
Driver OS supportn/a
User InterfaceAXI
IP-XACT Metadata includedN
Simulators supportedModelSim, RivieraPro
Hardware validated N. Altera Board Name NULL
Industry standard compliance testing performed
If No, is it planned?Y
IP has undergone interoperability testing
Interoperability reports available  N

Design Solutions Network Members provide products and/or services that are sold or licensed by the Member and not Intel® or its affiliates. Intel® and its affiliates hereby disclaim any express or implied warranty of any kind including warranties of merchantability, noninfringement of intellectual property, or fitness for any particular purpose with respect to any such products and/or services.