Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC
Stratix Series: Stratix® IV, Stratix® V
Supported Device Family:
IEEE 802.3bj was developed in response to the rapid growth of server,
network and internet traffic. The standard meets the need for higher
data rates over backplanes and copper cables for 100 Gbit/s throughput.
Device Utilization and Performance
100 Gbit/s coded throughput at 625 MHz.
Decoding latency of 92.8 ns at 625 MHz.
Latency of 1.6 ns at 625 MHz in bypass mode.
Bit Error Rate 10-11 at 8.8 dB at 8.8 dB (EB/N0)
Block Error Rate 10-8 at 8.7 dB at 8.7 dB (EB/N0)
Please contact Creonic Sales Team!
IP Quality Metrics
Year IP was first released
Latest version of Quartus supported
Altera Customer Use
IP has been successfully implemented in production with at least one customer
Customer deliverables include the following:
Design file (encrypted source code or post-synthesis netlist)
Simulation model for ModelSim Altera edition
Timing and/or layout constraints
Testbench or design example
Documentation with revision control
Any additional customer deliverables provided with IP
Parameterization GUI allowing end user to configure IP
IP core is enabled for OpenCore Plus Support
Software drivers provided
Driver OS support
IP-XACT Metadata included
N. Altera Board Name DE1, DE2
Industry standard compliance testing performed
If No, is it planned?
IP has undergone interoperability testing
Interoperability reports available
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