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Documentation

100 Gbit/s IEEE 802.3bj RS Encoder/ Decoder

Overview

Features

Device Utilization

Getting Started

IP Quality Metrics

Block Diagram

Solution Type: IP Core

End Market: Broadcast, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore Plus

Technology: DSP: Error Detection and Correction

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

Stratix Series: Stratix® IV, Stratix® V

Segments: 

Supported Device Family: 

Solution Type: 

Overview

IEEE 802.3bj was developed in response to the rapid growth of server, network and internet traffic. The standard meets the need for higher data rates over backplanes and copper cables for 100 Gbit/s throughput.

Features

    Device Utilization and Performance

    100 Gbit/s coded throughput at 625 MHz. Decoding latency of 92.8 ns at 625 MHz. Latency of 1.6 ns at 625 MHz in bypass mode. Bit Error Rate 10-11 at 8.8 dB at 8.8 dB (EB/N0) Block Error Rate 10-8 at 8.7 dB at 8.7 dB (EB/N0)

    Getting Started

    Please contact Creonic Sales Team!

    IP Quality Metrics

    Basic
    Year IP was first released2015
    Latest version of Quartus supported15.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY
    Deliverables

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    		 Y
    Any additional customer deliverables provided with IP
    		no
    Parameterization GUI allowing end user to configure IPN
    IP core is enabled for OpenCore Plus SupportY
    Source language
    		VHDL
    Testbench languageVHDL
    Software drivers providedN
    Driver OS supportn/a
    Implementation
    User InterfaceOther: proprietary
    IP-XACT Metadata includedN
    Verification
    Simulators supportedModelSim, RivieraPRO
    Hardware validated N. Altera Board Name DE1, DE2
    Industry standard compliance testing performed
    		N
    If No, is it planned?Y
    Interoperability
    IP has undergone interoperability testing
    		N
    Interoperability reports available  N

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