100 Gbit/s IEEE 802.3bj RS Encoder/ Decoder
Block Diagram

IP Quality Metrics
Basic | |
---|---|
Year IP was first released | 2015 |
Latest version of Quartus supported | 15.1 |
Altera Customer Use | |
IP has been successfully implemented in production with at least one customer | Y |
Deliverables | |
Customer deliverables include the following:
|
Y |
Any additional customer deliverables provided with IP | no |
Parameterization GUI allowing end user to configure IP | N |
IP core is enabled for OpenCore Plus Support | Y |
Source language | VHDL |
Testbench language | VHDL |
Software drivers provided | N |
Driver OS support | n/a |
Implementation | |
User Interface | Other: proprietary |
IP-XACT Metadata included | N |
Verification | |
Simulators supported | ModelSim, RivieraPRO |
Hardware validated | N. Altera Board Name NULL |
Industry standard compliance testing performed | N |
If No, is it planned? | Y |
Interoperability | |
IP has undergone interoperability testing | N |
Interoperability reports available | N |
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