DVB-T2 Modulator

Block Diagram

Solution Type: IP Core

End Market: Broadcast, Test & Measurement, Wireless

Evaluation Method: OpenCore Plus

Technology: DSP: Modulation and Demodulation

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

Stratix Series: Stratix® IV, Stratix® V


The DVB-T2 Modulator core provides a very efficient FPGA implementation of all functions required to modulate the output from a MPEG-2 transport multiplexer according to the DVB-T2 ETSI EN302 755. The DVB-T2 modulator core is compliant with the specification and fully supports 1K, 2K, 4K, 8K, 16K and 32K COFDM modes. The DVB-T2 core features an integrated normal- and short-frame length BCH/LDPC encoder. L1FIELD padding, encoding and puncturing are performed automatically. Support for single or multiple PLP network configurations, T2-Lite, T2MI and SFN profiles. For more up-to-date information about this core, please visit our website - http://www.commsonic.com/products/TDvbT2Modulator.htm


  • Compliant with DVB-T2 (EN 302 755)
  • Variable 1·7-10MHz bandwidth interpolation.
  • Integrated LDPC channel encoder with L1 field padding and puncturing.
  • SISO/MISO, single-PLP or multiple-PLP support.
  • Optional FEF, L1-ACE, PAPR-TR, T2MI, SFN support.

Device Utilization and Performance

Approximate size estimates for typical CMS0041 deployments targeting a selection of FPGA types are provided within the tables below. Estimates may change depending upon exact requirements, and synthesis customisations. Alternative FPGA targets may also be available, please contact Commsonic for further information.

Getting Started

Please contact Commsonic at info@commsonic.com for further information.

IP Quality Metrics

Year IP was first released2010
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportY
Source language
Testbench languageVHDL
Software drivers providedY
Driver OS supportC-code API
User InterfaceAvalon-MM
IP-XACT Metadata includedN
Simulators supportedModelsim
Hardware validated Y. Altera Board Name Cyclone-V Starter Kit.
Industry standard compliance testing performed
If No, is it planned?N
IP has undergone interoperability testing
Interoperability reports available  N

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