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Documentation

DVB-S2 / DVB-S2X Modulator

Block Diagram

Solution Type: IP Core

End Market: Broadcast, Test & Measurement, Wireless

Evaluation Method: OpenCore Plus

Technology: DSP: Modulation and Demodulation

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

Stratix Series: Stratix® IV, Stratix® V

Segments:

Supported Device Family:

Solution Type:

Overview

The CMS0025 DVB-S2 / -S2X (A)PSK modulator is an integrated modulator and channel-coder core designed specifically to address the requirements of the ETSI DVB-S2 forward-link satellite standard (EN302307) including the DVB-S2X extensions. The core can operate in CCM and VCM/ACM modes and is fully compliant with the standard. For further or more up-to-date information about this core, please visit our website - http://www.commsonic.com/products/SDvbS2Modulator.htm

Features

Compliant with DVB-S2 (EN 300 307-1) and DVB-S2X (EN 300 307-2)
Support for CCM, VCM and ACM modes.
Variable sample-rate interpolation provides ultra flexible clocking strategy.
QPSK, 8PSK, 16APSK, 32APSK, 64-APSK, 128-APSK and 256-APSK support.
Integrated LDPC Channel Coder.

Device Utilization and Performance

Approximate size estimates for typical CMS0025 deployments targeting a selection of FPGA types are provided within the tables below. Estimates may change depending upon exact requirements, and synthesis customisations. Alternative FPGA targets may also be available, please contact Commsonic for further information.

Getting Started

Please contact Commsonic at info@commsonic.com for further information.

IP Quality Metrics

Basic
Year IP was first released	2007
Latest version of Quartus supported	15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customer	Y
Deliverables
Customer deliverables include the following: Design file (encrypted source code or post-synthesis netlist) Simulation model for ModelSim Altera edition Timing and/or layout constraints Testbench or design example Documentation with revision control Readme file	Y
Parameterization GUI allowing end user to configure IP	Y
IP core is enabled for OpenCore Plus Support	Y
Source language	VHDL
Testbench language	VHDL
Software drivers provided	Y
Driver OS support	C-code API
Implementation
User Interface	Avalon-MM
IP-XACT Metadata included	N
Verification
Simulators supported	Modelsim
Hardware validated	Y. Altera Board Name Cyclone-III 3c25 Starter Kit.
Industry standard compliance testing performed	N
If No, is it planned?	N
Interoperability
IP has undergone interoperability testing	Y
Interoperability reports available	N

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