Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC
Stratix Series: Stratix® IV, Stratix® V
The CMS0048 has been designed from the ground-up for high-speed and gate-efficient implementation on FPGA and ASIC platforms and offers very high performance when combined with either the integrated FEC decoder or an external advanced FEC decoder.
The demodulator provides an adaptable starting point for receiver sub-systems to be used in both the current and next-generation of digital TV set-top-boxes, VSAT terminals and related test and monitoring equipment.
For further or more up-to-date information about this core, please visit our website - http://www.commsonic.com/products/SDvbSDemodulator.htm
Compliant with DVB-S (EN 300 421) and DVB-DSNG (EM 301 210)
QPSK, 8PSK, 16-QAM.
Variable symbol-rate interpolation from single clock reference.
All-digital timing and carrier recovery.
Automatic QAM mode, FEC and spectral inversion searching.
Device Utilization and Performance
Approximate size estimates for typical CMS0048 deployments targeting a selection of FPGA types are provided within the tables below. Estimates may change depending upon exact requirements, and synthesis customisations.
Alternative FPGA targets may also be available, please contact Commsonic for further information.
Please contact Commsonic at email@example.com for further information.
IP Quality Metrics
Year IP was first released
Latest version of Quartus supported
Altera Customer Use
IP has been successfully implemented in production with at least one customer
Customer deliverables include the following:
Design file (encrypted source code or post-synthesis netlist)
Simulation model for ModelSim Altera edition
Timing and/or layout constraints
Testbench or design example
Documentation with revision control
Parameterization GUI allowing end user to configure IP
IP core is enabled for OpenCore Plus Support
Software drivers provided
Driver OS support
IP-XACT Metadata included
Y. Altera Board Name Cyclone-V Starter Kit.
Industry standard compliance testing performed
If No, is it planned?
IP has undergone interoperability testing
Interoperability reports available
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