DVB-C / J83abc Demodulator

Block Diagram

Solution Type: IP Core

End Market: Broadcast, Test & Measurement, Wireline

Evaluation Method: OpenCore Plus

Technology: DSP: Modulation and Demodulation

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

Stratix Series: Stratix® IV, Stratix® V


The CMS0022 Cable (QAM) Demodulator is fully compliant with the European, US and Japanese downlink cable standards DVB-C EN 300 429 and ITU J83 Annexes A/B/C (including DOCSIS 1.1/2.0). The core provides all the necessary functions between modulated QAM input to transport stream output. J.83B designs can operate either from internal memory (short interleaving modes) or from shared external memory (long interleaving modes) by means of a versatile access controller. For more up-to-date information about this core, please visit our website - http://www.commsonic.com/products/CDVBCJ83Demodulator.htm


  • Compliant with DVB-C (EN 300 429) and ITU J.83 Annexes A, B and C including DOCSIS 1.1/2.0.
  • 16, 32, 64, 128 and 256 QAM.
  • Arbitrary symbol rate using a single master clock frequency.
  • Automatic QAM mode, FEC and spectral inversion searching.
  • Pre-Viterbi, Pre-RS and Post-FEC bit-error-rate statistics.

Device Utilization and Performance

Approximate size estimates for typical CMS0022 deployments targeting a selection of FPGA types are provided within the tables below. Estimates may change depending upon exact requirements, and synthesis customisations. Alternative FPGA targets may also be available, please contact Commsonic for further information.

Getting Started

Please contact Commsonic at info@commsonic.com for further information.

IP Quality Metrics

Year IP was first released2007
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportY
Source language
Testbench languageVHDL
Software drivers providedY
Driver OS supportC-code API
User InterfaceAvalon-MM
IP-XACT Metadata includedN
Simulators supportedModelsim
Hardware validated Y. Altera Board Name Cyclone-V Starter Kit.
Industry standard compliance testing performed
If No, is it planned?N
IP has undergone interoperability testing
Interoperability reports available  N

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