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Documentation

ATSC 8-VSB Modulator

Block Diagram

Solution Type: IP Core

End Market: Broadcast, Test & Measurement, Wireless

Evaluation Method: OpenCore, OpenCore Plus

Technology: DSP: Modulation and Demodulation

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

Stratix Series: Stratix® IV, Stratix® V

Segments:

Supported Device Family:

Solution Type:

Overview

The Commsonic multi-channel ATSC 8-VSB modulator (CMS0038) with integrated channel coders are designed specifically to implement the 8-VSB requirements of the ATSC Digital Television Standard (A/53). The core provides all the necessary processing for 8-VSB modulation of up to four transport streams. Supported output formats include baseband in-phase and quadrature (IQ) and IF. Every effort has been made to keep the size of the block to an absolute minimum in order to target the low-cost Intel® FPGA families;however this has not been at the expense of functionality. For further or more up-to-date information about this core, please visit our website - http://www.commsonic.com/products/TMcAtsc8VsbModulator.htm

Features

Compliant with ATSC A/53 8-VSB
Variable sample rate interpolation.
RS and convolutional encoding.
Segment/Field Sync and Pilot insertion.

Device Utilization and Performance

Approximate size estimates for typical CMS0038 deployments targeting a selection of FPGA types are provided within the tables below. Estimates may change depending upon exact requirements, and synthesis customisations.Alternative FPGA targets may also be available, please contact Commsonic for further information.

Getting Started

Please contact Commsonic at info@commsonic.com for further information.

IP Quality Metrics

Basic
Year IP was first released	2008
Latest version of Quartus supported	15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customer	Y
Deliverables
Customer deliverables include the following: Design file (encrypted source code or post-synthesis netlist) Simulation model for ModelSim Altera edition Timing and/or layout constraints Testbench or design example Documentation with revision control Readme file	Y
Parameterization GUI allowing end user to configure IP	Y
IP core is enabled for OpenCore Plus Support	Y
Source language	VHDL
Testbench language	VHDL
Software drivers provided	Y
Driver OS support	C-code API
Implementation
User Interface	Avalon-MM
IP-XACT Metadata included	N
Verification
Simulators supported	Modelsim
Hardware validated	Y. Altera Board Name Cyclone-III 3c25 Starter Kit.
Industry standard compliance testing performed	N
If No, is it planned?	N
Interoperability
IP has undergone interoperability testing	Y
Interoperability reports available	N

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