10M/100M/1G/2.5G Ethernet TSN MAC

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore Plus

Technology: Interface Protocols: Ethernet

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Stratix Series: Intel® Stratix® 10, Stratix® IV, Stratix® V

Overview

Comcores 10M/100M/1G/2.5G TSN MAC provides a complete IEEE 802.3 Ethernet Layer 2 solution with support for key TSN features including 802.1Qbu Preemption, 802.3br Interspersing Express Traffic, 802.1AS Timing and Synchronization and 802.1Qbv Enhancements for Scheduled Traffic. The TSN MAC enables deterministic low latency and guaranteed bandwidth for time sensitive applications. The TSN MAC allows flexibility in selecting a subset of standards depending on your application from industrial to automotive. The feature rich MAC-core that is delivered with SW API is a low latency cut-through implementation reaching best in market results while still keeping size at a minimum. The core is fully configurable and can optionally include features like IEEE1588, VLAN and DMA integration. The Ethernet MAC Core, on the Client side, implements two 8-bit asynchronous FIFO interfaces for Express and Preemptable traffic, respectively while having a standard MII/RGMII/GMII interface on the PHY side.

Features

  • FCS generation supported
  • Comprehensive statistics gathering
  • Supports VLAN and jumbo frames
  • Independent TX and RX Maximum Transmission Unit (MTU)
  • Very easy integration with standard AXI4 or APB interface

Device Utilization and Performance

MAC with Qbu (With default configuration-No optional feature included) ALM \t2755 REG \t3468 RAM \t32 DSP \t0 Device type used for estimate \tArria 10

Getting Started

Please contact Comcores Sales for further information

IP Quality Metrics

Basic
Year IP was first released2019
Latest version of Quartus supported18.0
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportN
Source language
VHDL
Testbench languageVHDL
Software drivers providedY
Driver OS supportLinux
Implementation
User InterfaceOther: AXI-S and Avalon-S
IP-XACT Metadata includedN
Verification
Simulators supportedSynopsys DC
Hardware validated Y. Altera Board Name Arria 10 SoC
Industry standard compliance testing performed
N
If No, is it planned?Y
Interoperability
IP has undergone interoperability testing
Y
Interoperability reports available  Y

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