10M/100M/1G/2.5G Ethernet TSN MAC
Block Diagram
Overview
Comcores 10M/100M/1G/2.5G TSN MAC provides a complete IEEE 802.3 Ethernet Layer 2 solution with support for key TSN features including 802.1Qbu Preemption, 802.3br Interspersing Express Traffic, 802.1AS Timing and Synchronization and 802.1Qbv Enhancements for Scheduled Traffic. The TSN MAC enables deterministic low latency and guaranteed bandwidth for time sensitive applications. The TSN MAC allows flexibility in selecting a subset of standards depending on your application from industrial to automotive. The feature rich MAC-core that is delivered with SW API is a low latency cut-through implementation reaching best in market results while still keeping size at a minimum. The core is fully configurable and can optionally include features like IEEE1588, VLAN and DMA integration. The Ethernet MAC Core, on the Client side, implements two 8-bit asynchronous FIFO interfaces for Express and Preemptable traffic, respectively while having a standard MII/RGMII/GMII interface on the PHY side.
IP Quality Metrics
| Basic | |
|---|---|
| Year IP was first released | 2019 |
| Latest version of Quartus supported | 18.0 |
| Altera Customer Use | |
| IP has been successfully implemented in production with at least one customer | Y |
| Deliverables | |
Customer deliverables include the following:
|
Y |
| Parameterization GUI allowing end user to configure IP | N |
| IP core is enabled for OpenCore Plus Support | N |
| Source language | VHDL |
| Testbench language | VHDL |
| Software drivers provided | Y |
| Driver OS support | Linux |
| Implementation | |
| User Interface | Other: AXI-S and Avalon-S |
| IP-XACT Metadata included | N |
| Verification | |
| Simulators supported | Synopsys DC |
| Hardware validated | Y. Altera Board Name Arria 10 SoC |
| Industry standard compliance testing performed | N |
| If No, is it planned? | Y |
| Interoperability | |
| IP has undergone interoperability testing | Y |
| Interoperability reports available | Y |
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