10G/25G Ethernet TSN MAC

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore Plus

Technology: Interface Protocols: Ethernet

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Stratix Series: Intel® Stratix® 10, Stratix® IV, Stratix® V

Overview

Comcores 10G/25G TSN MAC provides a complete IEEE 802.3 Ethernet Layer 2 solution with support for key TSN features including 802.1Qbu Preemption and 802.3br Interspersing Express Traffic. This enables the use of the MAC in high-speed time-critical applications. The MAC-core performs the Link function of the 10G/25G Ethernet Standard and is a low latency cut-through implementation reaching best in market results while still keeping size at a minimum. The core is fully configurable and interfaces easily to 10G/25G PCS. Features like IEEE1588 solution, VLAN and DMA integration can optionally be included. The Ethernet MAC Core, on the Client side, implements a 64-bit AXI-S interface for Express and Preemptable traffic respectively while having a standard XGMII interface on the PHY side.

Features

  • TSN features can be enabled/disabled independently
  • 802.1 AS extention available
  • Deficit Idle Count for maximum data throughput supported
  • In-Band FCS supported
  • Comprehensive statistics gathering

Device Utilization and Performance

MAC with Qbu: ALM 5802 REG 4905 RAM 28,5 49 DSP 0 Device type used for estimate Arria 10

Getting Started

Please contact Comcores Sales for more info

IP Quality Metrics

Basic
Year IP was first released2019
Latest version of Quartus supported18.0
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportN
Source language
VHDL
Testbench languageVHDL
Software drivers providedY
Driver OS supportLinux
Implementation
User InterfaceAXI
IP-XACT Metadata includedN
Verification
Simulators supportedSynopsys DC
Hardware validated Y. Altera Board Name Arria 10 SoC
Industry standard compliance testing performed
N
If No, is it planned?Y
Interoperability
IP has undergone interoperability testing
Y
Interoperability reports available  Y

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