ZipAccel-D: GUNZIP/ZLIB/Inflate Data Decompression Core

Block Diagram

Solution Type: IP Core

End Market: Computer & Storage, Consumer, Industrial, Military, Wireless, Wireline

Evaluation Method: OpenCore, OpenCore Plus

Technology: Processors and Peripherals: Peripherals

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

MAX Series: Intel® MAX® 10

Stratix Series: Stratix® IV, Stratix® V


ZipAccel-D is a custom hardware implementation of a lossless data decompression engine that complies with the Inflate/Deflate, GZIP/GUNZIP, and ZLIB compression standards.The megafunction features fast processing, with low latency and high throughput. On average the megafunction outputs two bytes of decompressed data per clock cycle, providing over 5Gbps in a typical 40nm technology. Designers can scale the throughput further by instantiating the megafunction multiple times to achieve throughput rates exceeding 100Gbps.The latency for blocks coded with Static Huffman is in the order offew tens of clock cycles, and blocks coded with Dynamic Huffman get processed in lessthan 1500 cycles.


  • Latency from a 20 clock cycles for Static Huffman blocks, and less than 1500 cycles for Dynamic Huffman Blocks
  • Up to 32KB history window size; All deflate block types
  • Throughputs exceeding 2Gbps in most FPGAs with a single core, and scalable to more than 100Gbps with multiple core instances
  • Compression Standards: ZLIB (RFC-1950); Inflate/Deflate (RFC-1951); GZIP/GUNZIP (RFC-1952)

Device Utilization and Performance

ZipAccel-D reference designs have been evaluated in a variety of technologies. ZipAccel-D performance can scale by instantiating more Huffman decoders and by using multiple megafunction instances. The core configured with Static Huffman only uses 2,281 ALMs and 20,160 RAM bits in an Intel® Arria® 10 device.

Getting Started

Contact CAST at to evaluate the core

IP Quality Metrics

Year IP was first released2011
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportY
Source language
Testbench languageVerilog
Software drivers providedN
Driver OS supportNone
User InterfaceAXI; Other: Streaming-capable i/f
IP-XACT Metadata includedN
Simulators supportedModelSim, Questa, NC-SIM
Hardware validated N. Altera Board Name NULL
Industry standard compliance testing performed
If No, is it planned?N
IP has undergone interoperability testing
Interoperability reports available  N

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