ZipAccel-D: GUNZIP/ZLIB/Inflate Data Decompression Core
Block Diagram
Segments:
Supported Device Family:
Solution Type:
Overview
ZipAccel-D is a custom hardware implementation of a lossless data decompression engine that complies with the Inflate/Deflate, GZIP/GUNZIP, and ZLIB compression standards.The megafunction features fast processing, with low latency and high throughput. On average the megafunction outputs two bytes of decompressed data per clock cycle, providing over 5Gbps in a typical 40nm technology. Designers can scale the throughput further by instantiating the megafunction multiple times to achieve throughput rates exceeding 100Gbps.The latency for blocks coded with Static Huffman is in the order offew tens of clock cycles, and blocks coded with Dynamic Huffman get processed in lessthan 1500 cycles.
Features
- Latency from a 20 clock cycles for Static Huffman blocks, and less than 1500 cycles for Dynamic Huffman Blocks
- Up to 32KB history window size; All deflate block types
- Throughputs exceeding 2Gbps in most FPGAs with a single core, and scalable to more than 100Gbps with multiple core instances
- Compression Standards: ZLIB (RFC-1950); Inflate/Deflate (RFC-1951); GZIP/GUNZIP (RFC-1952)
Device Utilization and Performance
ZipAccel-D reference designs have been evaluated in a variety of technologies. ZipAccel-D performance can scale by instantiating more Huffman decoders and by using multiple megafunction instances. The core configured with Static Huffman only uses 2,281 ALMs and 20,160 RAM bits in an Intel® Arria® 10 device.
IP Quality Metrics
| Basic | |
|---|---|
| Year IP was first released | 2011 |
| Latest version of Quartus supported | 15.1 |
| Altera Customer Use | |
| IP has been successfully implemented in production with at least one customer | Y |
| Deliverables | |
Customer deliverables include the following:
|
N |
| Parameterization GUI allowing end user to configure IP | N |
| IP core is enabled for OpenCore Plus Support | Y |
| Source language | Verilog |
| Testbench language | Verilog |
| Software drivers provided | N |
| Driver OS support | None |
| Implementation | |
| User Interface | AXI; Other: Streaming-capable i/f |
| IP-XACT Metadata included | N |
| Verification | |
| Simulators supported | ModelSim, Questa, NC-SIM |
| Hardware validated | N. Altera Board Name NULL |
| Industry standard compliance testing performed | N |
| If No, is it planned? | N |
| Interoperability | |
| IP has undergone interoperability testing | N |
| Interoperability reports available | N |
Design Solutions Network Members provide products and/or services that are sold or licensed by the Member and not Altera or its affiliates. Altera and its affiliates hereby disclaim any express or implied warranty of any kind including warranties of merchantability, noninfringement of intellectual property, or fitness for any particular purpose with respect to any such products and/or services.