Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC
MAX Series: Intel® MAX® 10, MAX® V
Stratix Series: Stratix® IV, Stratix® V
ZipAccel-C is a custom hardware implementation of a lossless data compression engine that complies with the Deflate, GZIP, and ZLIB compression standards. The megafunction receives uncompressed input files and produces compressed files. No post processing of the compressed files is required, as the megafunction encapsulates the compressed data payload with the proper headers and footers. Input files can be segmented, and segments from different files can be interleaved at themegafunction?s input.The megafunction's flexible architecture enables fine-tuning of its compression efficiency, throughput, and latency to match the requirements of the end application. Throughputs in excess of 100 Gbps are feasible even in low-cost FPGAs, and latency can be as small as a few tens of clock cycles.
ZipAccel-C reference designs have been evaluated in a variety of technologies. ZipAccel-C performance can scale by instantiating more search engines and/or Huffman decoders. Furthermore, other design options such as the search area window affect the silicon resources utilization. When configured with 1 Search Engine, 1 Dynamic Huffman Encoder, 4 KB History Window with a clock constraint of 200 MHz it uses 10,768 ALMs and 281,294 RAM bits in a Stratix® V device.
Contact CAST at email@example.com to evaluate the core
IP Quality Metrics
Year IP was first released
Latest version of Quartus supported
Altera Customer Use
IP has been successfully implemented in production with at least one customer
Customer deliverables include the following:
Design file (encrypted source code or post-synthesis netlist)
Simulation model for ModelSim Altera edition
Timing and/or layout constraints
Testbench or design example
Documentation with revision control
Any additional customer deliverables provided with IP
Bit Accurate Model
Parameterization GUI allowing end user to configure IP
IP core is enabled for OpenCore Plus Support
Software drivers provided
Driver OS support
AXI; Other: Streaming capable i/f
IP-XACT Metadata included
ModelSim, Questa, NC-SIM
N. Altera Board Name Various
Industry standard compliance testing performed
If No, is it planned?
IP has undergone interoperability testing
Interoperability reports available
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