WDR: Low-Power, Low-Latency HDR/WDR Image Processor

Block Diagram

Solution Type: IP Core

End Market: Automotive, Industrial, Medical, Military

Evaluation Method: OpenCore Plus

Technology: DSP: Video and Image Processing

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® V

Stratix Series: Intel® Stratix® 10, Stratix® V

Segments: 

Supported Device Family: 

Solution Type: 

Overview

The WDR core implements an efficient, low-power and low-latency High Dynamic Range (HDR) and Wide Dynamic Range (WDR) image processor that produces clear and sharp images under any lighting conditions. The core receives two, three, or four exposures of the same frame, in 10- or 12-bit RGB Bayer format and any resolution up to Full-HD. It processes the input with proprietary, content-adaptive algorithms for merging exposures, local and global tone mapping, and contrast expansion, and it also supports white-balance adjustment, optical back correction, and a 2D noise reduction filter. Being highly configurable and sensor-agnostic, the core addresses the needs of a wide range of applications. Run-time control over processing parameters enables users to adjust brightness, dynamic range, and sharpness to address the requirements of different use cases, and also provides the means to eliminate typical HDR/WDR processing artifacts such as flickering, shape deformation, and over-enhanced edges.

Features

  • Merges 2, 3 or 4 exposures and supports programmable exposure times and speed of response to content changes
  • Implements Local & Global Tone mapping, 2D Noise Reduction Filter and White Balancing Adjustment and Optical Black Correction
  • Low Latency & Low Power: Just seven lines of latency - Does not need power-consuming DDR
  • Sensor-Agnostic and Tunable to Application Requirements
  • Mass production proven, LINT-clean design

Device Utilization and Performance

The WDR core can be mapped to any Intel FPGA Device (provided sufficient silicon resources are available) and optimized to suit the particular project's requirements. The core requires approximately 30K ALMs, 80 RAM blocks and 91 DSP blocks when configured to support 1080p60 video. Please contact CAST to discuss resource utilization and performance for your application and target device.

Getting Started

Contact CAST at info@cast-inc.com to arrange for a core evaluation

IP Quality Metrics

Basic
Year IP was first released2016
Latest version of Quartus supported17.0
Altera Customer Use
IP has been successfully implemented in production with at least one customerN
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Any additional customer deliverables provided with IP
Software Bit Accurate Model
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog
Testbench languageVerilog
Software drivers providedN
Driver OS supportN/A
Implementation
User InterfaceOther: Standard sensor interface
IP-XACT Metadata includedN
Verification
Simulators supportedModelsim, Questa, NCSIM
Hardware validated Y. Altera Board Name Aria10 GX Devkit
Industry standard compliance testing performed
N
If No, is it planned?N
Interoperability
IP has undergone interoperability testing
N
Interoperability reports available  N

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