UDPIP-40G/50G: 40G/50G UDP/IP Hardware Protocol Stack
Block Diagram
Overview
The core is a UDP/IP hardware protocol stack. Designed for standalone operation, the core offloads the host processor from the task of UDP/IP encapsulation and enables media streaming with speeds up to 50Gbps even in processor-less designs. Trouble-free operation is ensured through run-time programmability of all the required network parameters (local, destination and gateway IP addresses; UDP ports; and MAC address). The core implements the ARP Protocol, which is critical for multiple access networks, and the Echo Request and Reply Messages of the ICMP widely used to test network connectivity. It can use a static IP address or automatically request and acquire an IP address from a DHCP server. Finally, the core supports 801.1Q tagging, and is suitable for operation in a Virtual LAN. The core is easy to integrate in systems with or without a host processor. Packet data can be read/written to the core via dedicated streaming-capable interfaces, or via registers mapped on an SoC bus.
Features
- Protocols, IPv4 without packet fragmentation, Jumbo and Super Jumbo Frames, ARP with Cache, ICMP (Ping), IGMP v3 (Multicast), UDP/IP Unicast and Multi
- 1 to 32 UDP transmit and 1 to UDP 32 receive channels
- Run time programmable network parameters: Local, Destination and Gateway IP address, Source and Destination UDP ports, MAC address
- Available pre-integrated with the Intel FPGA Ethernet MAC core
Device Utilization and Performance
The silicon resources requirements depend on the core configuration. A single channel core synthesizes to approximately 7,500 ALMs and requires 400k bits of memory, while a quad-channel core synthesizes to approximately 9,000 ALMs and requires 800k bits of memory. To deliver a 40Gbps under the worst-case scenario, the core needs to be clocked at 312.5MHz, however running the core at 200MHz should suffice to deliver 40Gbps in realistic UDP/IP traffic scenarios. To deliver 50Gbps under the worst-case scenario, the core needs to be clocked at 390.625MHz, however running the core at 250MHz should suffice to deliver 50Gbps in realistic UDP/IP traffic scenarios.
IP Quality Metrics
| Basic | |
|---|---|
| Year IP was first released | 2016 |
| Latest version of Quartus supported | 18.0 |
| Altera Customer Use | |
| IP has been successfully implemented in production with at least one customer | Y |
| Deliverables | |
Customer deliverables include the following:
|
Y |
| Any additional customer deliverables provided with IP | Wrapper integrating core with Intel FPGA Ethernet MAC |
| Parameterization GUI allowing end user to configure IP | N |
| IP core is enabled for OpenCore Plus Support | N |
| Source language | Verilog |
| Testbench language | Verilog |
| Software drivers provided | N |
| Driver OS support | Not required |
| Implementation | |
| User Interface | Other: AXI-Stream, or Avalon-ST |
| IP-XACT Metadata included | N |
| Verification | |
| Simulators supported | Modelsim, Questa, NCSIM |
| Hardware validated | Y. Altera Board Name StratixIV GX DevKit |
| Industry standard compliance testing performed | N |
| If No, is it planned? | N |
| Interoperability | |
| IP has undergone interoperability testing | N |
| Interoperability reports available | N |
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