UDPIP-100G: 100G UDP/IP Hardware Protocol Stack

Block Diagram

Solution Type: IP Core

End Market: Broadcast, Computer & Storage, Medical, Military, Test & Measurement, Wireline

Evaluation Method: OpenCore Plus

Technology: Interface Protocols: Ethernet

Arria Series: Intel® Arria® 10

Stratix Series: Intel® Stratix® 10

Overview

The UDPIP-100G is a 100Gbps UDP/IP hardware protocol stack. Designed for standalone operation, the core offloads the host processor from the task of UDP/IP encapsulation and enables communication with speeds up to 100Gbps even in processor-less designs. Trouble-free operation is ensured through run-time programmability of all the required network parameters (local, destination and gateway IP addresses; UDP ports; and MAC address). The core can use a static IP address or automatically request and acquire an IP address from a DHCP server. It also supports ARP, ICMP, IGMPv3, and VLAN (801.1Q tagging) without requiring any software assistance. The core is easy to integrate in systems with or without a host processor. Packet data can be read/written to the core via dedicated streaming-capable interfaces (up to 32 for Rx data and up to 32 for Tx Data), or via registers mapped on an SoC bus. \\

Features

  • Supports IPv4 without packet fragmentation, Jumbo and Super Jumbo Frames, ARP with Cache, ICMP (Ping), IGMP v3 (Multicast), UDP/IP Unicast and Multi
  • Up to 32 Rx and up to 32 Tx UDP channels
  • Run time programmable network parameters: Local, Destination and Gateway IP address, Source and Destination UDP ports, MAC address
  • 512-bit data-path and AXI-Stream data interfaces
  • Available pre-integrated with Intel’s 100G eMAC core

Device Utilization and Performance

The silicon resources requirements depend on the core configuration. A core configured with 1 receive and 1 transmit channels, 32kB transmit and receive buffers, and the Statistics Counters, Multicast. VLAN, and DHCP support disabled synthesizes to approximately 10,000 ALMs and 53 Blocks RAMs. A core configured with 16 receive and 16 transmit channels, 32kB transmit and receive buffers, and the Statistics Counters, Multicast. VLAN, and DHCP support enabled synthesizes to approximately 40,000 ALMs and 274 Blocks RAMs. To deliver a 100Gbps under the worst case scenario, the core needs to be clocked at 250MHz, however running the core at 200MHz should suffice to deliver 100Gbps in realistic UDP/IP traffic scenarios. Please contact CAST to get characterization data for your target configuration and device.

Getting Started

Contact CAST at info@cast-inc.com to arrange for a core evaluation

IP Quality Metrics

Basic
Year IP was first released2020
Latest version of Quartus supported18.0
Altera Customer Use
IP has been successfully implemented in production with at least one customerN
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog
Testbench languageVerilog
Software drivers providedN
Driver OS supportN/A
Implementation
User InterfaceAXI
IP-XACT Metadata includedY
Verification
Simulators supportedModelsim, Questa, NCSIM, VCS
Hardware validated Y. Altera Board Name PAC D5005
Industry standard compliance testing performed
N
If No, is it planned?N
Interoperability
IP has undergone interoperability testing
N
Interoperability reports available  Y

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