TSN-SE: TSN Ethernet Switched Endpoint Core
Block Diagram

Overview
The TSN-SE implements a switched endpoint controller suitable for the implementation of endpoints in-daisy-chained Time Sensitive Networking (TSN) Ethernet networks. It integrates hardware stacks for timing synchronization (IEEE 802.1AS), traffic shaping (IEEE 802.1Qav, IEEE 802.1Qbv), frame preemption (IEEE 802.1Qbu, IEEE 802.1Qbr), and a low-latency Ethernet MAC. The controller core is designed to enable high-precision timing synchronization, flexible yet accurate traffic scheduling and extremely low latency switching.
Features
- TSN Ethernet Switched Endpoint: Two Ethernet ports & one host processor port. Suitable for daisy-chained networks such as rings
- Integrates low-latency MAC, traffic scheduler, and time synchronization stack. Supports: IEEE 802.1Qav, Qbv, Qbu, Qbr, & IEEE 802.1AS
- Configurable, low Latency, cut-through switching
- Complete reference design available
Device Utilization and Performance
The TSN-ES core can be mapped to any Intel Device (provided sufficient silicon resources are available) and optimized to suit the particular project’s requirements. The size of the core depends on its configuration. Typical configurations occupy approximately 8,000 to 12,000 ALMs. Please contact CAST to discuss resource utilization and performance for your application and target device.
IP Quality Metrics
Basic | |
---|---|
Year IP was first released | 2020 |
Latest version of Quartus supported | 18.0 |
Altera Customer Use | |
IP has been successfully implemented in production with at least one customer | N |
Deliverables | |
Customer deliverables include the following:
|
Y |
Any additional customer deliverables provided with IP | gPTP lightweight stack |
Parameterization GUI allowing end user to configure IP | N |
IP core is enabled for OpenCore Plus Support | Y |
Source language | Verilog |
Testbench language | Verilog |
Software drivers provided | Y |
Driver OS support | Linux |
Implementation | |
User Interface | AXI |
IP-XACT Metadata included | N |
Verification | |
Simulators supported | Modelsim, Questa, NCSIM, VCS |
Hardware validated | Y. Altera Board Name Aria10-GX Devkit, Max 10 Devkit, NovTech Netleap |
Industry standard compliance testing performed | N |
If No, is it planned? | N |
Interoperability | |
IP has undergone interoperability testing | Y |
Interoperability reports available | N |
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