Cyclone Series:Intel® Cyclone® 10: Intel® Cyclone® 10 GX, Intel® Cyclone® 10 LP; Cyclone® IV, Cyclone® V, Cyclone® V SoC
MAX Series: Intel® MAX® 10
Stratix Series: Intel® Stratix® 10, Stratix® IV, Stratix® V
The TSN-EP implements an endpoint controller suitable for the implementation of endpoints in TSN Ethernet networks using a star topology. It integrates hardware stacks for timing synchronization (IEEE 802.1AS), traffic shaping (IEEE 802.1Qav, IEEE 802.1Qbv), frame preemption (IEEE 802.1Qbu, IEEE 802.1Qbr), and a low-latency Ethernet MAC. The controller core is designed to enable high-precision timing synchronization, flexible yet accurate traffic scheduling and extremely low latency switching.
The TSN-EP has been proven in several LNI 4.0 and IIC plugfests, and has been successfully deployed in several customer products.
TSN Ethernet Endpoint: One Ethernet ports & one host processor port. suitable for star-topology networks
Integrates low-latency MAC, traffic scheduler, and time synchronization stack. Supports: IEEE 802.1Qav, Qbv, Qbu, Qbr, & IEEE 802.1AS
The TSN-EP core can be mapped to any Intel Device (provided sufficient silicon resources are available) and optimized to suit the particular project’s requirements. The size of the core depends on its configuration. Typical configurations occupy 2,000 to 6,000 ALMs. Please contact CAST to discuss resource utilization and performance for your application and target device
Contact CAST at email@example.com to arrange for a core evaluation
IP Quality Metrics
Year IP was first released
Latest version of Quartus supported
Altera Customer Use
IP has been successfully implemented in production with at least one customer
Customer deliverables include the following:
Design file (encrypted source code or post-synthesis netlist)
Simulation model for ModelSim Altera edition
Timing and/or layout constraints
Testbench or design example
Documentation with revision control
Parameterization GUI allowing end user to configure IP
IP core is enabled for OpenCore Plus Support
Software drivers provided
Driver OS support
IP-XACT Metadata included
ModelSim, Questa, NC-SIM
Y. Altera Board Name Aria10-GX Devkit, Max 10 Devkit, NovTech Netleap
Industry standard compliance testing performed
If No, is it planned?
IP has undergone interoperability testing
Interoperability reports available
Design Solutions Network Members provide products and/or services that are sold or licensed by the Member and not Intel® or its affiliates. Intel® and its affiliates hereby disclaim any express or implied warranty of any kind including warranties of merchantability, noninfringement of intellectual property, or fitness for any particular purpose with respect to any such products and/or services.