Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC
MAX Series: Intel® MAX® 10
Stratix Series: Intel® Stratix® 10, Stratix® IV, Stratix® V
The SPMI-CTRL core implements a highly featured, easy-to-use controller for the MIPI System Power Management Interface (MIPI-SPMI) bus. It supports the latest version (v2.0) of the MIPI-SPMI specification and is suitable for the implementation of either master or slave nodes in an SPMI bus.
The core is designed to minimize the software load on the host processor. Once configured, the core requires no assistance from the host to initialize the bus, connect to bus or disconnect from the bus, grant access of the bus, execute incoming SPMI commands, generate ACK/NACK responses, and check the address and data parity. Although the core only expects the host to provide the outgoing SPMI commands, it provides thorough status information to the host.
Integration of the core is extremely simple: The core provides access to its registers via an AMBA™ 2 APB slave interface and converts the incoming SPMI read/write commands to accesses on its AHB master port.
MIPI-SPMI v2.0 Master or Slave: Supports High Speed (HS) and Low Speed (LS) device classes, all commands and all arbitration levels.
Low Host Overhead: Host is only required to initialize registers after a reset and define outgoing commands and arbitration levels
Run-time Debugging: Broadcasts SPMI bus state and device state, detects and reports errors, and can optionally captures all traffic in the SPMI bus
Easy Integration: Directly bridges SPMI and AHB bus address space, and allows register access via 32-bit AMBA™ 2 APB bus
Small and Low Power: Around 1,000 ALMs for either a master or a slave core, and direct serial clock usage to minimize switching activity when idle
Device Utilization and Performance
The SPMI-CTRL core can be mapped to any Intel FPGA Device (provided sufficient silicon resources are available) and optimized to suit the particular project's requirements. When configured as a master the core needs about 1,000 ALMs for its implementation. Approximately 850 ALMs are required for the implementation of slave core. Please contact CAST to discuss resource utilization and performance for your application and target device.
Contact CAST at firstname.lastname@example.org to arrange for a core evaluation
IP Quality Metrics
Year IP was first released
Latest version of Quartus supported
Altera Customer Use
IP has been successfully implemented in production with at least one customer
Customer deliverables include the following:
Design file (encrypted source code or post-synthesis netlist)
Simulation model for ModelSim Altera edition
Timing and/or layout constraints
Testbench or design example
Documentation with revision control
Any additional customer deliverables provided with IP
Parameterization GUI allowing end user to configure IP
IP core is enabled for OpenCore Plus Support
Software drivers provided
Driver OS support
Other: AHB and APB
IP-XACT Metadata included
Modelsim, Questa, NCSIM
Y. Altera Board Name Cyclone IV
Industry standard compliance testing performed
If No, is it planned?
IP has undergone interoperability testing
Interoperability reports available
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