SHA-3: SHA-3 Secure Hash Function Core
Block Diagram
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Overview
The SHA-3 IP core is a high-throughput, area-efficient hardware implementation of the SHA-3/Kaccak cryptographic hashing functions, compliant to NISTS's FIPS 180-4 and FIPS 202 standards.The core can implement any one of the four cryptographic SHA-3 hash functions provisioned by the standards: SHA3-224, SHA3-256, SHA3-384, and SHA3-512. Its throughput can optionally be optimized by using input message buffering, which allows it to receive new input while still processing the previous message. Also, the number of hashing rounds per clock is configurable at synthesis time, allowing users to constrain performance to save silicon resources when desired.The SHA-3 IP core can ensure data integrity and/or user authentication in a range of applications including IPsec and TLS/SSL protocol engines, encrypted data storage, secure processing systems, e-commerce, and financial transaction systems.
Features
- Standards: FIPS 202/SHA-3 - Permutation-Based Hash and Extendable-Output Function & FIPS 180-4/Secure Hash Functions (limited to SHA-3 use)
- Throughput: 48.0 Mbits/MHz for SHA3-224, 45.3 Mbits/MHz for SHA3-256, 34.7 Mbits/MHz for SHA3-384, 24.0 Mbits/MHz for SHA3-512
- Size: From 3,100 ALMs to 6,100 ALMs depending on configuration
- Configuration Options: Bit-width of input and output data buses, Number of input buffers, and Number of Hash rounds per cycle
Device Utilization and Performance
The core can be mapped to any Intel® FPGA Family and optimized to suit the particular project's requirements. The SHA-3 core synthesizes to about 3,000 ALMs when no buffers are implemented and from 4.3k ALMs (for SHA3-512) to 6.1k ALMs (for SHA3-224) when two input buffers are implanted. On an Arria10 device, the core can run at 150MHz providing a throughput of 7.2Gbps for SHA3-224, 6.8Gbps for SHA3-256, 5.2 Gbps for SHA3-384, and 3.6 Gbps for SHA3-512.
IP Quality Metrics
| Basic | |
|---|---|
| Year IP was first released | 2016 |
| Latest version of Quartus supported | 15.1 |
| Altera Customer Use | |
| IP has been successfully implemented in production with at least one customer | N |
| Deliverables | |
Customer deliverables include the following:
|
Y |
| Parameterization GUI allowing end user to configure IP | N |
| IP core is enabled for OpenCore Plus Support | Y |
| Source language | Verilog |
| Testbench language | Verilog |
| Software drivers provided | N |
| Driver OS support | Not required |
| Implementation | |
| User Interface | AXI |
| IP-XACT Metadata included | N |
| Verification | |
| Simulators supported | Modelsim, Questa, NCSIM |
| Hardware validated | N. Altera Board Name NULL |
| Industry standard compliance testing performed | N |
| If No, is it planned? | N |
| Interoperability | |
| IP has undergone interoperability testing | N |
| Interoperability reports available | N |
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