Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC
MAX Series: Intel® MAX® 10
Stratix Series: Intel® Stratix® 10, Stratix® IV, Stratix® V
The SFLASH-AHB core is a versatile SPI flash memory controller. It allows a system to easily access an SPI flash device or directly boot from it.
The core allows the system to interface with a flash device in one of the following modes: a) in Slave mode by accessing its registers, b) in DMA mode where the host programs the internal DMA engine, and then the core accordingly drives its AHB master interface, c) in XIP mode where the core allows the system to directly access the SPI memory address space via an AHB slave interface, d) in Boot-Image copy mode where after reset the core autonomously copies an amount of data from the flash to the AHB address space using its AHB master interface.
The device parameters can be set in two ways: a) via registers, where the host is to identify the connected flash device and program the core's registers, or b) by using the auto-configuration feature, where the core autonomously identifies the connected flash device and program itself accordingly.
SPI Flash controller supporting XIP and STR or DTR over single, dual, and quad SPI links.
Supports Boot-Image Copy: After reset the core uses its DMA engine to autonomously copy an amount of data from Flash to the AHB address space
Flash Device-Independent: Device parameters (including command en coding) are run-time programmable
Zero software overhead with XIP and auto-configuration
Fully configurable SPI interface: x1, x2 and x4 SPI, STR and DTR, 4 to 32 bit-word transmission pr date line, programmable SPI clock phase & polarity
Device Utilization and Performance
The SFLASH-AHB core can be mapped to any Intel FPGA Device (provided sufficient silicon resources are available) and optimized to suit the particular project's requirements. When configured without a DMA and without support for the auto-configuration mode the core needs about 1,000 ALMs for its implementation. Approximately 1,500 ALMs are required for the fully-featured core. Please contact CAST to discuss resource utilization and performance for your application and target device.
Contact CAST at firstname.lastname@example.org to arrange for a core evaluation
IP Quality Metrics
Year IP was first released
Latest version of Quartus supported
Altera Customer Use
IP has been successfully implemented in production with at least one customer
Customer deliverables include the following:
Design file (encrypted source code or post-synthesis netlist)
Simulation model for ModelSim Altera edition
Timing and/or layout constraints
Testbench or design example
Documentation with revision control
Parameterization GUI allowing end user to configure IP
IP core is enabled for OpenCore Plus Support
Software drivers provided
Driver OS support
Other: AHB 32-bit or 64-bit
IP-XACT Metadata included
Modelsim, Questa, NCSIM
Y. Altera Board Name DE0 Nano
Industry standard compliance testing performed
If No, is it planned?
IP has undergone interoperability testing
Interoperability reports available
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