SFLASH-AHB: Single, Dual, Quad, and Octal Flash Controller with XIP & DMA, for AHB

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Consumer, Industrial, Medical, Military, Test & Measurement, Wireline

Evaluation Method: OpenCore, OpenCore Plus

Technology: Memory Interfaces and Controllers: Flash

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

MAX Series: Intel® MAX® 10

Stratix Series: Intel® Stratix® 10, Stratix® IV, Stratix® V

Overview

The SFLASH-AHB core is a versatile SPI flash memory controller. It allows a system to easily access an SPI flash device or directly boot from it. The core allows the system to interface with a flash device in one of the following modes: a) in Slave mode by accessing its registers, b) in DMA mode where the host programs the internal DMA engine, and then the core accordingly drives its AHB master interface, c) in XIP mode where the core allows the system to directly access the SPI memory address space via an AHB slave interface, d) in Boot-Image copy mode where after reset the core autonomously copies an amount of data from the flash to the AHB address space using its AHB master interface. The device parameters can be set in two ways: a) via registers, where the host is to identify the connected flash device and program the core's registers, or b) by using the auto-configuration feature, where the core autonomously identifies the connected flash device and program itself accordingly.

Features

  • SPI Flash controller supporting XIP and STR or DTR over single, dual, quad, twin-quad, and octal SPI links.
  • Supports Boot-Image Copy: After reset the core uses its DMA engine to autonomously copy an amount of data from Flash to the AHB address space
  • Flash Device-Independent: Device parameters (including command en coding) are run-time programmable
  • Zero software overhead with XIP and auto-configuration
  • Fully configurable SPI interface: x1, x2 and x4 SPI, STR and DTR, 4 to 32 bit-word transmission pr date line, programmable SPI clock phase & polarity

Device Utilization and Performance

The SFLASH-AHB core can be mapped to any Intel FPGA Device (provided sufficient silicon resources are available) and optimized to suit the particular project's requirements. When configured without a DMA and without support for the auto-configuration mode the core needs about 1,000 ALMs for its implementation. Approximately 1,500 ALMs are required for the fully-featured core. Please contact CAST to discuss resource utilization and performance for your application and target device.

Getting Started

Contact CAST at info@cast-inc.com to arrange for a core evaluation

IP Quality Metrics

Basic
Year IP was first released2016
Latest version of Quartus supported17.0
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog
Testbench languageVerilog
Software drivers providedN
Driver OS supportN/A
Implementation
User InterfaceOther: AHB 32-bit or 64-bit
IP-XACT Metadata includedNULL
Verification
Simulators supportedModelsim, Questa, NCSIM
Hardware validated Y. Altera Board Name DE0 Nano
Industry standard compliance testing performed
N
If No, is it planned?N
Interoperability
IP has undergone interoperability testing
N
Interoperability reports available  N

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