Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC
MAX Series: Intel® MAX® 10
Stratix Series: Stratix® IV, Stratix® V
Supported Device Family:
The SCR core implements an interface and controller for communicating between smart cards and host systems using a variety of standard system interfaces.
The SCR supports the ISO/IEC 7816-3:1997(E) and EMV2000 4.0 specifications, which define the electrical signals and transmission protocols for smart cards (also known as integrated circuit cards). It acts as a communication controller, passing data to and from the host system and the smart card. It is fully-featured, and can activate and deactivate cards, perform cold/warm resets, handle ATR response reception, and execute other essential functions.
The SCR consists of the core smart card reader logic with a wrapper for the desired system interface. (AMBA APB and Wishbone interfaces are available; support for other bus interfaces is optional.)
Supports the ISO/IEC 7816-3:1997(E) and EMV’2000 4.0 specifications, and synchronous and any other non-ISO 7816 and non-EMV’96 or EMV2000 cards
Performs functions needed for complete sessions, including: Card activation and deactivation, cold/warm reset, ATR response reception, data transfers
Configurable timing functions: Smart card activation time, Guard time and Timeout timers
Supports automatic convention detection, automatic voltage class selection, automatic byte repetition and handles commonly used communication protocol
Features an extensive interrupt support system, adjustable clock rate and bit (baud) rate, and adjustable FIFOs for Receive and Transmit buffers
Device Utilization and Performance
The core synthesizes to about 750 LEs.
Contact CAST at firstname.lastname@example.org to arrange for a core evaluation
IP Quality Metrics
Year IP was first released
Latest version of Quartus supported
Altera Customer Use
IP has been successfully implemented in production with at least one customer
Customer deliverables include the following:
Design file (encrypted source code or post-synthesis netlist)
Simulation model for ModelSim Altera edition
Timing and/or layout constraints
Testbench or design example
Documentation with revision control
Parameterization GUI allowing end user to configure IP
IP core is enabled for OpenCore Plus Support
Software drivers provided
Driver OS support
IP-XACT Metadata included
ModelSim, Questa, NC-SIM
N. Altera Board Name DE0 Nano
Industry standard compliance testing performed
If No, is it planned?
IP has undergone interoperability testing
Interoperability reports available
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