QSPI-XIP: SPI/QSPI Flash Controller with XIP

Block Diagram

Solution Type: IP Core

End Market: Automotive, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore Plus

Technology: Interface Protocols: Serial

eASIC™ Series: Intel® eASIC™ N2X, Intel® eASIC™ N2XT, Intel® eASIC™ N3X, Intel® eASIC™ N3XS

Arria Series: Intel® Arria® 10, Arria® V, Arria® V SoC

Cyclone Series: Intel® Cyclone® 10: Intel® Cyclone® 10 GX, Intel® Cyclone® 10 LP; Cyclone® IV, Cyclone® V, Cyclone® V SoC

MAX Series: Intel® MAX® 10

Stratix Series: Intel® Stratix® 10, Stratix® IV, Stratix® V

Overview

The QSPI-XIP core implements a quad Serial Peripheral Interface (SPI) module that either controls a serial data link as a master, or reacts to a serial data link as a slave. Users can configure the core via software control to be a master or slave device. In master mode, it can be used with up to four SPI slave devices. The QSPI-XIP core is compatible with various industry-standard DMA controllers. Enabling DMA operation assists a DMA controller in the loading (writing) of the transmit FIFO, and the unloading (reading) of the receive FIFO. Reading and writing the core is done via an AMBA® AHB or AXI slave interface. The Execute in Place (XIP) Mode allows a bus master to directly read the contents of any of several industry-standard flash devices (such as Winbond, Macronix, Spansion, and Micron devices) simply by reading from the address space of the QSPI Controller.

Features

  • SPI Flash controller supporting XIP over single, dual, and quad SPI links.
  • Fully configurable SPI interface: x1, x2 and x4 SPI, 4 to 32 bit-word transmission per date line, programmable SPI clock phase & polarity
  • Supports Motorola Serial Peripheral Interface (SPI), TI Synchronous Serial Frame, and National Microwire Frame formats
  • Master or Slave mode; controls up to four slaves in Master mode

Device Utilization and Performance

The QSPI-XIP core can be mapped to any Intel FPGA Device (provided sufficient silicon resources are available) and optimized to suit the particular project’s requirements. Approximately 3,500 ALMs are required for the fully-featured core. Please contact CAST to discuss resource utilization and performance for your application and target device.

Getting Started

Contact CAST at info@cast-inc.com to arrange for a core evaluation

IP Quality Metrics

Basic
Year IP was first released2017
Latest version of Quartus supported18.0
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Any additional customer deliverables provided with IP
None
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog
Testbench languageVerilog
Software drivers providedN
Driver OS supportN/A
Implementation
User InterfaceAXI; Other: AHB (optional)
IP-XACT Metadata includedN
Verification
Simulators supportedModelsim, Questa, NCSIM, VCS
Hardware validated Y. Altera Board Name Arria10-GX Devkit
Industry standard compliance testing performed
N
If No, is it planned?N
Interoperability
IP has undergone interoperability testing
Y
Interoperability reports available  N

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